Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet

Sherazi, Syed Muhammad Yasser; Cupak, M.; Weckx, Pieter; Zografos, Odysseas; Jang, Doyoung; Debacker, Peter; Verkest, D.; Mocuta, A.; Kim, R. H.; Spessot, A.; Ryckaert, Julien

doi:10.1117/12.2514569

Cited by 13 publications

(7 citation statements)

References 3 publications

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“…We set the number of masks for each BEOL according to [7]. We use 36nm and 24nm for the contacted poly pitches (CPPs)/M1 pitch and M0/M2 metal pitches, respectively, by applying the design parameters from [2] 5 .…”

Section: Resultsmentioning

confidence: 99%

“…Fig. 7 shows that the cell width increases by 75% with the EOL=1 for 1-tier AND2x2 VFET cell 7 . Therefore, VFET requires EOL=0 to achieve the maximum area reduction over the conventional structure.…”

Section: Single Cell Comparisonsmentioning

confidence: 99%

“…The horizontal pin-cost (HP) and vertical pin-cost (VP) are defined as the sum of the number of adjacent I/O pins within an interference distance d int in the horizontal and vertical directions as shown in ( 5) and (6), relatively. The number of T M (i.e., top metal layer) tracks is defined as the number of occupied top-metal layer routing tracks in a generated cell as shown in (7). The total metal length (ML) is the weighted sum of the routed metal segments as shown in (8) 3 .…”

Section: Multi-objective Optimizationmentioning

confidence: 99%

“…However, designing an optimal-layout standard cell is nontrivial and extremely laborious since it requires to explore enormously large search space combined with complicated constraints from transistor-level placement and incell routing. Therefore, the automation of standard cell (SDC)layout design takes essential roles for achieving seamless technology transition and design-based equivalent scaling through manufacturability-aware standard cell layout design [7], [8]. Conventional SDC Synthesis.…”

Section: Introductionmentioning

confidence: 99%

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Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

Lee

Kang

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Many-tier vertical gate-all-around nanowire FET (VFET) synthesis strongly demands a holistic approach of modeling/formulating/optimizing transistor placement and in-cell routing to obtain the maximum-achievable PPAC (power, performance, area, and cost) benefits. In this paper, we propose a novel SMT (Satisfiability Modulo Theories)-based many-tier VFET standard cell (SDC) synthesis framework that simultaneously solves place-and-route (P&R). We devise an extended relative positioning constraint and a dummy gate control scheme to capture the unique VFET cell architecture. Moreover, we present efficient objectives to improve pin-accessibility and reduce the use of vertical routing, which has high resistance. Compared to the conventional sequential P&R approach, our concurrent P&R achieves a 15.2% smaller cell area on average for 2tier VFET. Throughout the extensive exploration for many-tier VFET configurations up to 4-tier, we show that the 4-tier VFET respectively achieves 50.1% and 27.9% of average area reduction on chip-level and block-level, over 4.5T GAAFET.

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Section: Resultsmentioning

confidence: 99%

Section: Single Cell Comparisonsmentioning

confidence: 99%

Section: Multi-objective Optimizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

Lee

Kang

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…Technology scaling has driven the phenomenal success of the semiconductor industry in delivering more complex, faster, and cheaper integrated circuits with a high quality of service [1]. Silicon technology has entered the nano-era and transistors with sizes below 5 nm are being prototyped [2,3]. However, it is widely recognized that defects and variability in device characteristics during the fabrication process, and their impact on the overall quality and reliability of the system represent major challenges, especially when considering high-quality levels, e.g., in the range of defective parts per billion (DPPB) [4].…”

Section: Introductionmentioning

confidence: 99%

Device-Aware Test: A New Test Approach Towards DPPB Level

Fieback

Medeiros

et al. 2019

2019 IEEE International Test Conference (ITC)

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This paper proposes a new test approach that goes beyond cell-aware test, i.e., device-aware test. The approach consists of three steps: defect modeling, fault modeling, and test/DfT development. The defect modeling does not assume that a defect in a device (or a cell) can be modeled electrically as a linear resistor (as the traditional approach suggests), but it rather incorporates the impact of the physical defect on the technology parameters of the device and thereafter on its electrical parameters. Once the defective electrical model is defined, a systematic fault analysis (based on fault simulation) is performed to derive appropriate fault models and subsequently test solutions. The approach is demonstrated using two memory technologies: resistive random access memory (RRAM) and spintransfer torque magnetic random access memory (STT-MRAM). The results show that the proposed approach is able to sensitize faults for defects that are not detected with the traditional approach, meaning that the latter cannot lead to high-quality test solutions as required for a defective part per billion (DPPB) level. The new approach clearly sets up a turning point in testing for at least the considered two emerging memory technologies.

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CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation

Cheng

Kahng

Kang

et al. 2021

2021 IEEE 39th International Conference on Computer Design (ICCD)

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Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet

Cited by 13 publications

References 3 publications

Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

Device-Aware Test: A New Test Approach Towards DPPB Level

CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation

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