Standards-compliant IP-based ASIC and SoC design

Hekmatpour, Amir; Goodnow, K.; Shah, Hairol Nizam Mohd

doi:10.1109/socc.2005.1554521

Cited by 4 publications

(2 citation statements)

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“…IP modules are used for improving productivity in [Zergainoh et al 2005]. In [Hekmatpour et al 2005], a methodology is described for IP design and integration. The above mentioned studies mainly consider the library based design for design of application-specific circuits or reduce compilation time for the FPGA design flow based on hard macros consisting of synthesized, placed and routed circuits.…”

Section: Introductionmentioning

confidence: 99%

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration

Mao

Chen

Zhang

et al. 2016

ACM Trans. Des. Autom. Electron. Syst.

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While traditional Field-Programmable Gate Array design flow usually employs fine-grained tile-based placement, modular placement is increasingly required to speed up the large-scale placement and save the synthesis time. Moreover, the commonly used modules can be pre-synthesized and stored in the library for design reuse to significantly save the design, verification time, and development cost. Previous work mainly focuses on modular floorplanning without module placement information. In this article, we propose a library-based placement and routing flow that best utilizes the pre-placed and routed modules from the library to significantly save the execution time while achieving the minimal area-delay product. The flow supports the static and reconfigurable modules at the same time. The modular information is represented in the B*-Tree structure, and the B*-Tree operations are amended together with Simulated Annealing to enable a fast search of the placement space. Different width-height ratios of the modules are exploited to achieve area-delay product optimization. Partial reconfiguration-aware routing using pin-to-wire abutment is proposed to connect the modules after placement. Our placer can reduce the compilation time by 65% on average with 17% area and 8.2% delay overhead compared with the fine-grained results of Versatile Place and Route through the reuse of module information in the library for the base architecture. For other architectures, the area increase ranges from 8.32% to 25.79%, the delay varies from − 13.66% to 19.79%, and the runtime improves by 43.31% to 77.2%.

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Section: Introductionmentioning

confidence: 99%

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration

Mao

Chen

Zhang

et al. 2016

ACM Trans. Des. Autom. Electron. Syst.

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show abstract

“…IP modules are used for improving productivity in [ZPJU05]. In [HGS05], a methodology is described for IP design and integration. The above mentioned studies mainly consider the library based design for design of application-specific circuits or reduce compilation time for the FPGA design flow based on hard macros consisting of synthesized, placed and routed circuits.…”

Section: Introductionmentioning

confidence: 99%

Design automation flow for partial run-time reconfiguration on FPGAs

Mao¹

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SOC design for wireless communications

Stamenković

2010

2010 12th Biennial Baltic Electronics Conference

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The paper emphasizes methods, architectures and components for system-on-chip design. It describes the basic knowledge and skills for designing high-performance low-power embedded devices whose complexity increases exponentially, as so does the effort of designing them. Relying upon an appropriate design methodology which concentrates on reuse, executable specifications, and early error detection, these complexities can be mastered. The paper bundles these topics in order to provide a good understanding of all problems involved. It shows how to go from description and verification to implementation and testing presenting two systems-on-chip for two different wireless applications based on configurable processors and custom hardware accelerators.

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Standards-compliant IP-based ASIC and SoC design

Cited by 4 publications

References 1 publication

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration

Design automation flow for partial run-time reconfiguration on FPGAs

SOC design for wireless communications

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