State-of-the-art pipeline A/D converter survey and analysis

Abstract

This paper surveys and analyzes state-of-the-art pipeline A/D Converter reported in IEEE from 1987 to June 2011, including performance comparison of these converters on the ground of Resolution, Sampling Rate, Power, Spurious Free Dynamic Range (SFDR), and Signal to Noise plus Distortion Ratio (SNDR)/ Signal to Noise and Distortion Ratio (SINAD). Technological and architectural progress brings low power, low voltage high sampling rate pipeline A/D converter though the resolution being constant over the period. We found that power consumption of pipeline A/D converter decreased 1.62mW/month, sampling frequency increased 360 KHz/month, improvement of SFDR is approximately stagnant, and SNDR decreased 0.127dB/month over the time.

Progress in Data Acquisition of Wearable Sensors

“…The data quantized by the ADC is fed to the DAC for processing, and the analog input is then subtracted from the sampled input, resulting in a residual voltage that goes through the accumulator (G) to the next stage. The pipeline ADC has a high conversion rate and low power consumption, which is widely used in high-speed and high-precision fields such as wireless communication and digital video [ 97 ]. However, its complex bias structure and high circuit process requirements, as well as the delay in the signal traversal through the digital circuit [ 98 ], make it unsuitable for simple, sensitive wearable sensors.…”