State-restrict MLC STT-RAM designs for high-reliable high-performance memory system

Wen, Wujie; Zhang, Yaojun; Mao, Mengjie; Chen, Yiran

doi:10.1109/dac.2014.6881362

Cited by 13 publications

(13 citation statements)

References 20 publications

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“…(1) while not empty do (2) if there is an V with degree ≤ then (3) delete V (4) else (5) obtain the frequency set by offline profiling (6) sort variables based on the descending write cost (7) choose V with MAX COST (8) add V to spilling list (9) delete V (10) end if (11) if no variable has been spilled then (12) color the variables in reverse order of deleting (13) else (14) spill each V ∈ everywhere (15) rebuild the interference graph and repeat the procedure (16) end if (17) end while Algorithm 2: SSCM-based register allocation algorithm. Thus, all accesses take the same amount of time.…”

Section: Methodsmentioning

confidence: 99%

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State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

Gong

Chen

et al. 2017

VLSI Design

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Multilevel Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) is a promising nonvolatile memory technology to build registers for its natural immunity to electromagnetic radiation in rad-hard space environment. Unlike traditional SRAM-based registers, MLC STT-RAM exhibits unbalanced write state transitions due to the fact that the magnetization directions of hard and soft domains cannot be flipped independently. This feature leads to nonuniform costs of write states in terms of latency and energy. However, current SRAM-targeting register allocations do not have a clear understanding of the impact of the different write state-transition costs. As a result, those approaches heuristically select variables to be spilled without considering the spilling priority imposed by MLC STT-RAM. Aiming to address this limitation, this paper proposes a state-transition-aware spilling cost minimization (SSCM) policy, to save power when MLC STT-RAM is employed in register design. Specifically, the spilling cost model is first constructed according to the linear combination of different state-transition frequencies. Directed by the proposed cost model, the compiler picks up spilling candidates to achieve lower power and higher performance. Experimental results show that the proposed SSCM technique can save energy by 19.4% and improve the lifetime by 23.2% of MLC STT-RAM-based register design.

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Section: Methodsmentioning

confidence: 99%

“…Two MTJs with different sizes are stacked vertically atop an NMOS transistor. The four resistance states are defined by the four combinations of different MDs of the two MTJs [9].…”

Section: Mlc Stt-ram Preliminariesmentioning

confidence: 99%

State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

Gong

Chen

et al. 2017

VLSI Design

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“…MLC write operations as demonstrated earlier are slower and energy-consuming compared with the SLC case. During the past few decades, several encoding methods have been proposed to reduce write energy and increase STT-MRAM lifetime [20][21][22][23][24][25][26][27][28][29][30][31][32][33]. Since, both read energy and latency of STT-MRAM are very low, replacing a write operation with a read-modify-write operation is an efficient way to reduce energy consumption.…”

Section: Related Workmentioning

confidence: 99%

“…Such ternary cache enhances the reliability of MLC cache while maintaining good data density characteristics. A similar three-value STT-MRAM technique was proposed by Wen et al [28] to mitigate read and write errors.…”

Section: Related Workmentioning

confidence: 99%

Extending multi‐level STT‐MRAM cell lifetime by minimising two‐step and hard state transitions in hot bits

Ahmad

Imdoukh

Alfailakawi

2017

IET Computers & Digital Techniques

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Shifting market trends towards mobile, Internet of things, and data-centric applications create opportunities for emerging low-power non-volatile memories. The attractive features of spin-torque-transfer magnetic-RAM (STT-MRAM) make it a promising candidate for future on-chip cache memory. Two-bit multiple-level cell (MLC) STT-MRAMs suffer from higher write energy, performance overhead, and lower cell endurance when compared with single-level counterpart. These unwanted effects are mainly due to write operations known as two-step (TT) and hard transitions (HT). Here, the authors offer a solution to tackle write energy problem in MLC STT-MRAM by minimising the number of TT and HT transitions. By analysing real applications, it was observed that specific locations within a cache block undergo much more TT and HT transitions resulting in hot locations when compared with other ones (cold locations). These hot locations are more detrimental to the lifetime and reliability of MRAM device. In this work, the authors propose a simple and intuitive dynamic encoding scheme that eliminates all TT and HT at hot locations, hence reducing energy consumption and improving MLC STT-MRAM lifetime. Results on PARSEC benchmarks demonstrate the effectiveness and scalability of the proposed approach to potentially prolong MLC STT-MRAM lifetime.

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“…However, to the best of our knowledge, FVE has not been applied to MLC/TLC NVMs, where a single physical cell can store more than one logical bit to realize density and cost advantages [15,16]. Since MLC/TLC NVMs have higher write energy and access latency as well as lower endurance in comparison to SLC NVMs, there is strong motivation to develop data encoding and wear-leveling techniques for MLC/TLC NVMs [9,10,[17][18][19].…”

Section: Introductionmentioning

confidence: 99%

An Offline Frequent Value Encoding for Energy-Efficient MLC/TLC Non-volatile Memories

Alsuwaiyan

Mohanram

2016

Proceedings of the 26th Edition on Great Lakes Symposium on VLSI

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This paper describes a low overhead, offline frequent value encoding (FVE) solution to reduce the write energy in multi-level/triplelevel cell (MLC/TLC) non-volatile memories (NVMs). The proposed solution, which does not require any runtime software support, clusters a set of general-purpose applications according to their data frequency profiles and generates a dedicated offline FVE that minimizes write energy for each cluster. Results show that the write energy reduction of evaluation sets-using FVEs generated for training sets-are close (equal) to the best known solution for MLC (TLC) NVM encoding; however, our solution incurs a memory overhead that is 16× (5.7×) less than the best comparable scheme in the literature for MLC (TLC) NVMs.

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State-restrict MLC STT-RAM designs for high-reliable high-performance memory system

Cited by 13 publications

References 20 publications

State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

Extending multi‐level STT‐MRAM cell lifetime by minimising two‐step and hard state transitions in hot bits

An Offline Frequent Value Encoding for Energy-Efficient MLC/TLC Non-volatile Memories

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