Static identification of delinquent loads

Panait, Vlad-Mihai; Sasturkar, Amit; Wong, Weng-Fai

doi:10.1109/cgo.2004.1281683

Cited by 17 publications

(23 citation statements)

References 13 publications

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“…Empirically, we have observed that a small number of load instructions account for more than 90% of the total data stalls that a program suffers (see Table 1). Our results are in accord with prior work [2,31] that also observed the number of delinquent loads in a program is small when compared to the total number of loads in the same program. This characteristic allows the prefetching system to focus the memory optimizations to a manageable set of instructions, and indeed, we exploit this characteristic in our work.…”

Section: Delinquent Load Selectionsupporting

confidence: 83%

Compiler orchestrated prefetching via speculation and predication

et al. 2004

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This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. We focus the scope of the optimization on specific subsets of the program dependence graph that succinctly characterize the memory access pattern of both regular array-based applications and irregular pointer-intensive programs. We illustrate how program embedded precomputation via speculative execution can accurately predict and effectively prefetch future memory references with negligible overhead. The proposed techniques reduce the total running time of seven SPEC benchmarks and two OLDEN benchmarks by 27% on an Itanium 2 processor. The improvements are in addition to several state-of-the-art optimizations including software pipelining and data prefetching. In addition, we use cycle-accurate simulations to identify important and lightweight architectural innovations that further mitigate the memory system bottleneck. In particular, we focus on the notoriously challenging class of pointerchasing applications, and demonstrate how they may benefit from a novel scheme of sentineled prefetching. Our results for twelve SPEC benchmarks demonstrate that 45% of the processor stalls that are caused by the memory system are avoidable. The techniques in this paper can effectively mask long memory latencies with little instruction overhead, and can readily contribute to the performance of processors today.

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Section: Delinquent Load Selectionsupporting

confidence: 83%

Compiler orchestrated prefetching via speculation and predication

et al. 2004

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“…Our technique identifies exactly those load and store instructions that tend to cause many cache misses. Panait et al [6] proposed a technique to statically identify the load instructions that cause many cache misses. They call such a load instruction a delinquent load.…”

Section: Related Workmentioning

confidence: 99%

Identifying the sources of cache misses in Java programs without relying on hardware counters

InoueHiroshi

NakataniToshio

2012

SIGPLAN Not.

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Cache miss stalls are one of the major sources of performance bottlenecks for multicore processors. A Hardware Performance Monitor (HPM) in the processor is useful for locating the cache misses, but is rarely used in the real world for various reasons. It would be better to find a simple approach to locate the sources of cache misses and apply runtime optimizations without relying on an HPM. This paper shows that pointer dereferencing in hot loops is a major source of cache misses in Java programs. Based on this observation, we devised a new approach to identify the instructions and objects that cause frequent cache misses. Our heuristic technique effectively identifies the majority of the cache misses in typical Java programs by matching the hot loops to simple idiomatic code patterns. On average, our technique selected only 2.8% of the load and store instructions generated by the JIT compiler and these instructions accounted for 47% of the L1D cache misses and 49% of the L2 cache misses caused by the JIT-compiled code. To prove the effectiveness of our technique in compiler optimizations, we prototyped object placement optimizations, which align objects in cache lines or collocate paired objects in the same cache line to reduce cache misses. For comparison, we also implemented the same optimizations based on the accurate information obtained from the HPM. Our results showed that our heuristic approach was as effective as the HPMbased approach and achieved comparable performance improvements in the SPECjbb2005 and SPECpower_ssj2008 benchmark programs.

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“…Previous research [19,20,22,30] has demonstrated various compiler optimizations capable of automatically analyzing delinquent loads from a program and generating effective data-prefetching helper threads. The register partitioning optimization geared towards achieving minimal VMT thread switch overhead is yet another enhancement to such optimizing compiler infrastructure development.…”

Section: Fly-weight Vmt Thread Context Switchmentioning

confidence: 99%

Helper threads via virtual multithreading on an experimental itanium ^® 2 processor-based platform

Wang

Collins

Wang

et al. 2004

SIGOPS Oper. Syst. Rev.

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Helper threading is a technology to accelerate a program by exploiting a processor's multithreading capability to run "assist" threads. Previous experiments on hyper-threaded processors have demonstrated significant speedups by using helper threads to prefetch hard-to-predict delinquent data accesses. In order to apply this technique to processors that do not have built-in hardware support for multithreading, we introduce virtual multithreading (VMT), a novel form of switch-on-event user-level multithreading, capable of fly-weight multiplexing of event-driven thread executions on a single processor without additional operating system support. The compiler plays a key role in minimizing synchronization cost by judiciously partitioning register usage among the user-level threads. The VMT approach makes it possible to launch dynamic helper thread instances in response to long-latency cache miss events, and to run helper threads in the shadow of cache misses when the main thread would be otherwise stalled.The concept of VMT is prototyped on an Itanium r 2 processor using features provided by the Processor Abstraction Layer (PAL) firmware mechanism already present in currently shipping processors. On a 4-way MP physical system equipped with VMT-enabled Itanium 2 processors, helper threading via the VMT mechanism can achieve significant performance gains for a diverse set of real-world workloads, ranging from single-threaded workstation benchmarks to heavily multithreaded large scale decision support systems (DSS) using the IBM DB2 Universal Database. We measure a wall-clock speedup of 5.8% to 38.5% for the workstation benchmarks, and 5.0% to 12.7% on various queries in the DSS workload. † Dongkeun Kim is currently a Ph.D. candidate in the Department of Electrical and

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Static identification of delinquent loads

Abstract: The effective use of processor caches is crucial to the performance of applications. It

Cited by 17 publications

References 13 publications

Compiler orchestrated prefetching via speculation and predication

Compiler orchestrated prefetching via speculation and predication

Identifying the sources of cache misses in Java programs without relying on hardware counters

Helper threads via virtual multithreading on an experimental itanium ^® 2 processor-based platform

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Static identification of delinquent loads

Abstract: The effective use of processor caches is crucial to the performance of applications. It

Cited by 17 publications

References 13 publications

Compiler orchestrated prefetching via speculation and predication

Compiler orchestrated prefetching via speculation and predication

Identifying the sources of cache misses in Java programs without relying on hardware counters

Helper threads via virtual multithreading on an experimental itanium ® 2 processor-based platform

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Helper threads via virtual multithreading on an experimental itanium ^® 2 processor-based platform