Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)

Park, T.; Cho, H.J.; Choe, Jeong-Dong; Han, Sang-Wook; Jung, Seung Min; Jeong, Jae Hoon; Nam, B.Y.; Kwon, Oh-Hyun; Han, Jeonghoon; Kang, Hee Sun; Chae, Moosung; Yeo, Gi-Sung; Lee, S.W.; Lee, D.Y.; Park, D.; Kim, K.; Yoon, Eunchul; Lee, J.H.

doi:10.1109/iedm.2003.1269158

Cited by 17 publications

(4 citation statements)

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“…To consider a lightly doping channel, the substrate doping concentration of SOI FinFET is 3 × 10 16 cm −3 . To eliminate the short channel effects, we note that the setting on SOI FinFET's silicon fin thickness and the channel length has resulted in an optimal geometry aspect ratio (fin thickness/channel length) [6,7,9,10,11,12,13,14]. A nearly undoped channel will reduce the effect of random dopant on the device performance [23].…”

Section: Resultsmentioning

confidence: 99%

“…For 45nm fabrication technologies, planar MOSFETs encounter significant challenges to device performance and circuit stability [2,3,4]. The SRAM with diverse device structures, such as the thin-buried-oxide SOI MOSFETs and SOI FinFETs have been of great interest [5,6,7,8] due to good suppression of shortchannel effects and high area's efficiency [9,10,11,12,13,14]. Study of SNM for SRAM with the 32nm planar MOSFETs and SOI FinFETs helps technological development.…”

Section: Introductionmentioning

confidence: 99%

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Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors

Hwang

2007

Computational Science – ICCS 2007

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Abstract. We in this paper for the first time explore the static noise margin (SNM) of a six-transistor (6T) static random access memory (SRAM) cell with nanoscale silicon-on-insulator (SOI) fin-typed field effect transistors (FinFETs). The SNM is calculated with respect to the supply voltage, operating temperature, and cell ratio by performing a three-dimensional mixed-mode simulation. To include the quantum mechanical effect, the density-gradient equation is simultaneously solved in the coupled device and circuit equations. The standard deviation (σSNM ) of SNM versus device's channel length is computed, based upon the design of experiment and response surface methodology. Compared with the result of SNM for SRAM with 32nm planar metal-oxide-semiconductor field effect transistors, SRAM with SOI FinFETs quantitatively exhibits higher SNM and lower σSNM . Improvement of characteristics resulting from good channel controllability implies that SRAM cells fabricated with FinFETs continuously maintains cell stability in sub-32nm technology nodes.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors

Hwang

2007

Computational Science – ICCS 2007

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“…However, with SNM ∼ 140 mV and I wr ∼ 15 µA, the 2WL 6-T SRAM cell shows promising performance down to V DD = 0.5 V, demonstrating excellent scalability with power supply. Figure 12 compares our projected SNM values for the 2WL 6-T SRAM cell with state-of-the-art experimental data for SOI/SON [56][57][58][59][60][61][62][63][64], DG/FinFETs [65][66][67][68][69][70][71] and multibridge channel (MBC) FET [72][73][74] technologies over a wide range of gate lengths and supply voltages. Our optimized lowleakage SRAM cell (based on double-gate FET) fits in very well with the SNM trend emerging from the experimental data of DG/FinFETs.…”

Section: Valuementioning

confidence: 99%

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

Rashmi

Kranti

Armstrong

2008

Semicond. Sci. Technol.

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2008). 6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology. Semiconductor Science and Technology, 23 (7), [075049]. https://doi. AbstractThe impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/σ ) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM ∼ 162 mV, I wr ∼ 35 µA and low I leak ∼ 70 pA at V DD = 0.6 V, while maintaining SNM ∼ 30%V DD over the supply voltage (V DD ) range of 0.4-0.9 V.

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“…Recently, the body-tied triple-gate fin field-effect transistors (bulk FinFETs) [1][2][3][4] built on bulk silicon (Si) wafer have been considered as a very promising candidate for future nanoscale CMOS devices. Bulk FinFETs have the advantages such as low cost, low defect density, no floating-body effect, high heat transfer rate to the substrate, and nearly the same process flow as conventional bulk CMOS technology over silicon-on-insulator (SOI) FinFETs while keeping nearly the same scaling-down characteristics as those of the SOI FinFETs.…”

Section: Introductionmentioning

confidence: 99%

Current–Voltage Model of Bulk Fin Field-Effect Transistors with a Half-Circle Corner

Choi

Jeong

Kwon

et al. 2013

Jpn. J. Appl. Phys.

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The drain current of fully depleted (FD) nanoscale bulk FinFETs with the top-channel of a half-circle shape was modeled, for the first time, systematically in all operational regions and compared with the data obtained from three-dimensional (3D) device simulation. In the current model of these devices, it is very important to have accurate threshold voltages for side-channels and top-channel, and take the field penetration effect induced by the top-gate near the top of a fin body into account the threshold voltage (V th) models for top-channels and side-channels, respectively. So, we obtained successfully the V th models [V th0t (V th model of top-channel at a low drain bias) and V th0s (V th model of side-channels at a low drain bias)] considering the field penetration effect for both channels (top- and side-channels) to model the current behaviors in the doped bulk FinFETs with the top-channel of a half-circle shape. Our compact current model with V th0t and V th0s predicted accurately the current behaviors of the devices and shown a good agreement with 3D simulation.

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Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)

Cited by 17 publications

References 0 publications

Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors

Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

Current–Voltage Model of Bulk Fin Field-Effect Transistors with a Half-Circle Corner

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