Static Proton and Heavy Ion Testing of the Xilinx Virtex-5 Device

Quinn, Heather; Morgan, Keith S.; Graham, Paul; Krone, J.; Caffrey, Michael

doi:10.1109/redw.2007.4342561

Cited by 56 publications

(36 citation statements)

References 1 publication

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“…One possible explanation is that presumably the arrangement of BRAM cells is not the same in the row and column direction. A previous generation of SRAM-based FPGA (Virtex-5) presented similar effects to angles of incidence and rotation irradiation [15]. Fig.…”

Section: B Effect Of Incident Angle At Similar Letmentioning

confidence: 63%

Analyzing the Influence of the Angles of Incidence and Rotation on MBU Events Induced by Low LET Heavy Ions in a 28-nm SRAM-Based FPGA

Tonfat

Kastensmidt

Artola

et al. 2017

IEEE Trans. Nucl. Sci.

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Section: B Effect Of Incident Angle At Similar Letmentioning

confidence: 63%

Analyzing the Influence of the Angles of Incidence and Rotation on MBU Events Induced by Low LET Heavy Ions in a 28-nm SRAM-Based FPGA

Tonfat

Kastensmidt

Artola

et al. 2017

IEEE Trans. Nucl. Sci.

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“…For each orbit, the SER is estimated for different solar conditions as: Worst Week, Worst Day, Peak Five Minutes, and Solar Max conditions of a Solar Energetic Particle (SEP) event [42], [47] for the Xilinx Virtex-5 XUPV5LX110T FPGA [49], using the CREME96 tools [44]. We believe that the estimations are reliable because the selected FPGA's technology has been largely studied in the literature against different sources of radiation [50], [51]. By using the documentation provided by the manufacturer and by carrying out experimental measurements, it was possible to calculate the reconfiguration overhead of tasks in this device.…”

Section: A Experimental Setupmentioning

confidence: 99%

Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch

Ramezani

Sedaghat

Clemente

2017

IEEE Trans. VLSI Syst.

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Abstract-This study presents a technique to improve the reliability and the Mean Time to Failure (MTTF) of hardware task graphs running on reconfigurable computers. This technique, which has been named Task Early-fetch, can be applied to a sequence of one or several applications, represented as task graphs. It consists in carrying out the reconfiguration of some tasks within the execution of the previous task graph, plus increasing the redundancy level of the early-fetched tasks. Experimental results on actual task graphs show the positive impacts of the proposed technique. Thus, without deteriorating the execution time (makespan), on average, a 114% MTTF improvement is achieved for no-fault-tolerant task graphs, and the improvement is more significant when applying to faulttolerant task graphs. Finally, this paper presents a hardware implementation of a manager that applies these techniques at run-time and steers the execution of the running task graphs. It demonstrates that, with 0.03% consumption of FFs and LUTs and also 1.22% occupancy of BRAMs available on a Xilinx Virtex UltraScale XCVU095-2FFVA2104E FPGA, the required run-time computations can be carried out in negligible delays.

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“…In [Quinn et al 2007c] they present the results regarding circuitry to which TMR is applied and discuss the problem of domain crossing errors. In [Quinn et al 2007b], first results for Virtex-5 are published. In 2009, results regarding the SEUsusceptibility of logical constants were presented [Quinn et al 2009a].…”

Section: Accelerated Radiation Testingmentioning

confidence: 99%

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Siegle

Vladimirova

Ilstad³

et al. 2015

ACM Comput. Surv.

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The use of static random access memory (SRAM)-based field programmable gate arrays (FPGAs) in harsh radiation environments has grown in recent years. These types of programmable devices require special mitigation techniques targeting the configuration memory, the user logic, and the embedded RAM blocks. This article provides a comprehensive survey of the literature published in this rich research field during the past 10 years. Furthermore, it can also serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.

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Static Proton and Heavy Ion Testing of the Xilinx Virtex-5 Device

Abstract: This paper presents proton and heavy ion static results for the latest Xilinx field-programmable gate arrays (FPGAs). The paper analyzes static bit cross-sections, resources, multiple-bit upsets (MBUs) and angular effects.

Cited by 56 publications

References 1 publication

Analyzing the Influence of the Angles of Incidence and Rotation on MBU Events Induced by Low LET Heavy Ions in a 28-nm SRAM-Based FPGA

Analyzing the Influence of the Angles of Incidence and Rotation on MBU Events Induced by Low LET Heavy Ions in a 28-nm SRAM-Based FPGA

Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

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