Statistical Analysis of 5T SRAM Cell for Low Power and Less Area SRAM Based Cache Memory for IoT Applications

Prasad, Govind; Mandi, Bipin Chandra; Ramu, Patha; Sowrabh, Tirumala V.; Kumar, Anumula Harish

doi:10.1109/icpc2t48082.2020.9071468

Cited by 10 publications

(1 citation statement)

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“…The SRAM stores each bit by using bi-stable latching circuitry [4]. The measure of data stability of the SRAM is defined by the static noise margin (SNM), which is the minimum voltage noise that can flip its state [5]. A larger SNM ensures that the contents of the cell are unaltered during the read access, while allowing the cell to rapidly change its state across the write operation.…”

Section: Introductionmentioning

confidence: 99%

A Comparative Performance Analysis of 6T & 9T SRAM Integrated Circuits: SOI vs. Bulk

Khan¹,

Perdriau²,

Ramdani³

et al. 2022

IEEE Lett. on Electromagn. Compat. Pract. and Appl.

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This paper evaluates the performance of 6T & 9T static random access memory (SRAM) cells, for data stability and power metrics, with the aim to compare silicon-on-insulator (SOI) and bulk CMOS technologies. Each SRAM topology was designed & simulated in 180 nm 5 V XFAB-SOI and AMS-bulk processes, using optimized parameters and compatible devices. The fundamental variables analyzed were read noise margins, write trip current & voltage as well as leakage current (LC) and static power dissipation (SPD) under process and temperature (PT) variations. The static noise margin (SNM) butterfly curve and N-curve methodologies were used to assess the mentioned parameters. Compared to bulk technology, the SRAM cells designed with SOI were found to have lower SPD & LC, higher data stability, lower write ability, larger sensitivity to process variations and higher resilience to temperature deviations.

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Section: Introductionmentioning

confidence: 99%