Statistical analysis of process variation induced SRAM electromigration degradation

Guan, Zhong; Marek-Sadowska, Malgorzata; Nassif, Sani R.

doi:10.1109/isqed.2014.6783395

Cited by 12 publications

(6 citation statements)

References 26 publications

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“…We evaluated four different memory bit-cells with each being designed at the same condition of 10 ns switching time; 2 ns sensing time; 15% write margin; defined as (I W -I C )/I C ; and >40% read-disturb margin, defined as (I C -I R )/I C , in an array comprising 256 rows and 512 columns [29][30][31]. See Table 2 for simulation results.…”

Section: Simulation Resultsmentioning

confidence: 99%

Area Optimization Techniques for High-Density Spin-Orbit Torque MRAMs

Seo

Kwon

2021

Electronics

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This paper presents area optimization techniques for high-density spin-orbit torque magnetic random-access memories (SOT-MRAMs). Although SOT-MRAM has many desirable features of nonvolatility, high reliability and low write energy, it poses challenges to high-density memory implementation because of the use of two access transistors per cell. We first analyze the layout of the conventional SOT-MRAM bit-cell that includes two vertical metal lines, a bit-line and a source-line, limiting the horizontal dimension. We further propose two design techniques to reduce the horizontal dimension by decreasing the number of metal lines per cell without any performance overhead. Based on the fact that adjacent columns in a bit-interleaved array are not simultaneously accessed, the proposed techniques share a single source-line between two consecutive bit-cells in the same row. The simulation result shows that proposed techniques can achieve a bit-cell area reduction of 10–25% compared to the conventional SOT-MRAM. The comparison of our proposed designs with the standard spin-transfer torque MRAM shows 45% lower write energy, 84% lower read energy, and 2.3 × higher read-disturb margin.

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Section: Simulation Resultsmentioning

confidence: 99%

Area Optimization Techniques for High-Density Spin-Orbit Torque MRAMs

Seo

Kwon

2021

Electronics

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“…During read/write operations, the unbalanced currents flowing over interconnects cause voids which ultimately lead to operation failure by introducing large delay. In [129][130][131], the authors designed a methodology for SRAM EM reliability assessment with considering process variations. The equivalent current distributions over bitlines are calculated with an AFDbased current conversion scheme.…”

Section: Modeling Of Em Impact On Interconnects In Cache Memorymentioning

confidence: 99%

Recent Progress in Physics-Based Modeling of Electromigration in Integrated Circuit Interconnects

2022

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The advance of semiconductor technology not only enables integrated circuits with higher density and better performance but also increases their vulnerability to various aging mechanisms which occur from front-end to back-end. Analysis on the impact of aging mechanisms on circuits’ reliability is crucial for the design of reliable and sustainable electronic systems at advanced technology nodes. As one of the most crucial back-end aging mechanisms, electromigration deserves research efforts. This paper introduces recent studies on physics-based modeling of electromigration aging of on-chip interconnects. At first, the background of electromigration is introduced. The conventional method and physics-based modeling for electromigration are described. Then studies on how electromigration affects powers grids and signal interconnects are discussed in detail. Some of them focus on the comprehensiveness of modeling methodology, while others aim at the strategies for improving computation accuracy and speed and the strategies for accelerating/decelerating aging. Considering the importance of electromigration for circuit reliability, this paper is dedicated to providing a review on physics-based modeling methodologies on electromigration and their applications for integrated circuits interconnects.

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“…The existing works on EM analysis in the signal lines of SRAM [9,10] are based on Blech length formulation, which is too simplistic. They do not consider the impact of various material parameters given in the Korhonen's equation on the EM failure times.…”

Section: Em Modelingmentioning

confidence: 99%

“…However, it has been shown that even signal lines in Static Random Access Memory (SRAM) can have EM failures [9,10]. These works focus on EM analysis for the read operation in SRAM, since the read current is unidirectional and hence self-healing effect is smaller.…”

Section: Introductionmentioning

confidence: 99%

“…In this work, we investigate the EM failures in the bit- Such workload-based analysis has been ignored in the previous studies. In addition, the existing EM modeling in signal lines for SRAM [9,10] is based on simple Blech length formulation. In contrast, in this work, we perform EM analysis using the physics-based EM model developed in our previous works [11,12], which is calibrated based on industrial measurement data.…”

Section: Introductionmentioning

confidence: 99%

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Workload-Aware Electromigration Analysis in Emerging Spintronic Memory Arrays

Nair

Mayahinia

Tahoori

et al. 2021

IEEE Trans. Device Mater. Relib.

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Electromigration (EM) has emerged as a major reliability concern for interconnects in advanced technology nodes. Most of the existing EM analysis works focus on the power lines. There exists a limited amount of work which analyzes EM failures in the signal lines. However, various emerging spintronicbased memory technologies such as the Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) and the Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) have high current densities as compared to the conventional Static Random Access Memory (SRAM). These high current densities can lead to EM failures in the signal lines such as bit-line (BL) of these memories. Furthermore, these signal lines have workloaddependent stress as opposed to the conventional DC stress of power distribution networks. In this work, we model the EM failures in the BL of a typical STT memory array with realistic workloads. The analysis is based on physics-based EM model, which is calibrated based on industrial measurement data. The results show that the current densities in the STT arrays can be large enough to cause EM failures in the signal lines with running realistic workloads and that these failures are highly workload-dependent.

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Statistical analysis of process variation induced SRAM electromigration degradation

Cited by 12 publications

References 26 publications

Area Optimization Techniques for High-Density Spin-Orbit Torque MRAMs

Area Optimization Techniques for High-Density Spin-Orbit Torque MRAMs

Recent Progress in Physics-Based Modeling of Electromigration in Integrated Circuit Interconnects

Workload-Aware Electromigration Analysis in Emerging Spintronic Memory Arrays

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