Statistical integrated circuit design

Feldmann, P.; Krishna, K.

doi:10.1109/4.209985

Cited by 83 publications

(25 citation statements)

References 23 publications

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“…Response surface methods (RSM) [13] are strongly related to our approach. Previous works reporting on design optimization with RSM [8], [5] use linear or quadratic fits. Dealing with complex models, these parametric fits can only be used as local approximations.…”

Section: Introductionmentioning

confidence: 99%

Model-Based Design Analysis and Yield Optimization

Pfingsten

Herrmann

Rasmussen

2006

IEEE Trans. Semicond. Manufact.

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Abstract-Fluctuations are inherent to any fabrication process. Integrated circuits and micro-electro-mechanical systems are particularly affected by these variations, and due to high quality requirements the effect on the devices' performance has to be understood quantitatively. In recent years it has become possible to model the performance of such complex systems on the basis of design specifications, and model-based Sensitivity Analysis has made its way into industrial engineering. We show how an efficient Bayesian approach, using a Gaussian process prior, can replace the commonly used brute-force Monte Carlo scheme, making it possible to apply the analysis to computationally costly models. We introduce a number of global, statistically justified sensitivity measures for design analysis and optimization. Two models of integrated systems serve us as case studies to introduce the analysis and to assess its convergence properties. We show that the Bayesian Monte Carlo scheme can save costly simulation runs and can ensure a reliable accuracy of the analysis.

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Section: Introductionmentioning

confidence: 99%

Model-Based Design Analysis and Yield Optimization

Pfingsten

Herrmann

Rasmussen

2006

IEEE Trans. Semicond. Manufact.

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“…The application-level accuracy-robustness synthesis methodology presented in this paper shows strong affinity with the integrated circuits yield maximization problem (which requires maximization of the yield subject to design constraints [12]- [15]). To some extent, the two problems, which are clearly on separate abstraction levels, can be formally cast in a similar optimization framework provided that "yield" is suitably substituted with "perturbation space volume" and "design constraint" with "accuracy constraint," respectively.…”

Section: Introductionmentioning

confidence: 99%

An application-level synthesis methodology for multidimensional embedded processing systems

Alippi

Galbusera

Stellini

2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The implementation of multidimensional systems in embedded devices is a major design challenge due to the high algorithmic complexity of the applications. The authors suggest a novel application-level synthesis methodology for those parts of the embedded application which are characterized by being Lebesgue measurable (the computation involved in signal and image processing systems is Lebesgue measurable). The synthesis methodology, based on perturbation analysis, supports the design of analog, digital, or mixed implementations at the very high level of the system design cycle. The outputs of the methodology are quantitative indications regarding the maximum performance loss tolerable by the subsystems composing the application. Such information, augmented with a stochastic description of the tolerated perturbations, can be related to lower synthesis levels and guide the designer toward the final implementation of the embedded device. The perturbation analysis is based on randomized algorithms for an effective evaluation of the performance loss of the computational flow once affected by behavioral perturbations and a Tabu-search-inspired optimizing algorithm for distributing the tolerable performance loss at the system output along the computational subsystems composing the possibly multidimensional processing.

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“…Early developments are known under the heading "statistical design" [12]. Problems for which specific variation-aware techniques have been proposed include transistor sizing [7], yield optimization [5] and voltage binning [46].…”

Section: A Variation-aware Designmentioning

confidence: 99%

Towards Variation-Aware Test Methods

Polian

Becker

Hellebrand

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE.

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Statistical integrated circuit design

Cited by 83 publications

References 23 publications

Model-Based Design Analysis and Yield Optimization

Model-Based Design Analysis and Yield Optimization

An application-level synthesis methodology for multidimensional embedded processing systems

Towards Variation-Aware Test Methods

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