Statistical Metallurgical Model for Electromigration Failure in Aluminum Thin-Film Conductors

Attardo, M. J.; Rutledge, Richard E.; Jack, R. C.

doi:10.1063/1.1659778

Cited by 122 publications

(19 citation statements)

References 7 publications

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“…These peculiarities grow with time in chaotic order [241,242]. As a result, the metal line is covered by cells of voids and pileup of metal material accumulation.…”

Section: Electromigrationmentioning

confidence: 99%

Physical Limitations of Semiconductor Devices

Ващенко¹,

Sinkevitch²

2008

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“…These peculiarities grow with time in chaotic order [241,242]. As a result, the metal line is covered by cells of voids and pileup of metal material accumulation.…”

Section: Electromigrationmentioning

confidence: 99%

Physical Limitations of Semiconductor Devices

Ващенко¹,

Sinkevitch²

2008

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“…Model extraction was done following the method of Meeker and Escobar [16], using Splida statistical analysis software [17]. Electromigration failure data for silicon interconnect have historically been analyzed using a lognormal distribution [18], but there is also evidence that this distribution may lead to overly optimistic projections at the low end of the failure distribution [19]. Both lognormal and Weibull distributions have been used to analyze bump electromigration data [2,20,21].…”

Section: Figure 3 Cross Section Of a Failed Bump Showing Severe Voimentioning

confidence: 99%

Geometry Effects on the Electromigration of Eutectic SN/PB Flip-Chip Solder Bumps

Eaton

Rowatt

Dauksher

2006

2006 IEEE International Reliability Physics Symposium Proceedings

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This work investigates the effect of passivation opening diameter and underbump metallization (UBM) diameter on the electromigration (EM) resistance of Sn/Pb eutectic solder bumps. For the bump geometries studied, the electromigration lifetime depends strongly on the UBM area but weakly on the passivation opening area. The applicability of Black's model for extrapolating lifetime from accelerated currents to operating currents is investigated. The thermal activation energy, E A , is approximately 1.0 eV and the current density exponent, n, is approximately 2.0. While Black's model for current density acceleration appears to apply, the current density exponent may not be transferable between bumps of different geometries. A physical model of voiding within the bump using finite element analysis is proposed to explain the observed results.

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“…The issue of weak links and early failures in Albased interconnects has been an active research topic for a number of years. 6,7,[31][32][33][34][35][36][37][38][39] An example might be the presence of nonbamboo grains along a chain of bamboo grains in a narrow Al(Cu) interconnect. The presence of early failures in small amounts in an interconnect population would be undetectable in the small samplings (20 or so) typically used for EM testing.…”

Section: Weakest Link Approximation and Failure Distributionsmentioning

confidence: 99%

Reliability and early failure in Cu/oxide dual-damascene interconnects

Ogawa

Lee

Matsuhashi

et al. 2002

Journal of Elec Materi

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The drive toward greater device density and higher performance in Si-based microelectronics technology has led to the recent transition to newer backend interconnect materials. However, this transition must be accomplished without sacrificing the reliability requirements necessary for long-term product functionality. 1,2 The recent introduction of Cu metallization to replace Al(Cu) technology is one example, 3 but the transition will also later require the incorporation of new and often exotic low-k interlevel and intralevel dielectrics as well as ultrathin Cu DB materials. The rapid introduction of new materials in advanced integrated circuit technology is in marked contrast to the seemingly less turbulent prior history-at least from a materials perspective-in microelectronics. All this materials change will also be done under a new interconnect integration architecture: the single-damascene (SD) and dual-damascene (DD) processes. The impact of these new materials and integration scheme on interconnect reliability, such as electromigration (EM) and stress-induced voiding, is still presently not well understood, and the literature on Cu/low-k reliability is still rather sparse. Yet, the knowledgebase is growing, and certain aspects of the effect of the damascene architecture on at least EM reliability are becoming clearer. DD Interconnects: Basic ArchitectureThe basic layout of a Cu-based, submicron, twolevel interconnect suitable for study of EM phenomena in DD systems is shown in Fig. 1a. The DD interconnect is placed at the upper metal level (M2), while a SD interconnect is used at the lower level metal (M1). The Cu metal is surrounded by a thin Ta diffusion barrier (DB) around its sides and bottom and by a capping layer (CL, typically SiN x ) on top. A typical barrier thickness may range between 100 and 300 Å, but the thickness on the via sidewall may be thinner by, say, 25-50%. The CL thickness is typically in the range of 1000 Å. The specific thickness dimensions of these films may vary depending on the technology node targeted. An intralevel dielectric material (ILD, for example, CVD-based SiO x glass) lies between the metal lines. Both the ILD and CL are targeted as regions where the introduction of new lower-k materials will be necessary for future device performance improvements. The M1 and M2 interconnects are electrically connected through the via V1, which is processed as a continuous part of the M2 interconnect.In EM studies on DD interconnects, two current flow directions must be considered. The first electron Recent results on up-direction electromigration (EM) studies on Cu dual-damascene (DD) interconnects are presented. The issue of the DD process and its potential effect on EM reliability is described with special focus on the peculiarities of the DD interconnect architecture in comparison to the previous subtractively etched Al-based interconnect technology. Experiments performed on multilink, DD interconnects that highlight EM reliability issues, such as early failure, and the Blech effect a...

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Statistical Metallurgical Model for Electromigration Failure in Aluminum Thin-Film Conductors

Cited by 122 publications

References 7 publications

Physical Limitations of Semiconductor Devices

Physical Limitations of Semiconductor Devices

Geometry Effects on the Electromigration of Eutectic SN/PB Flip-Chip Solder Bumps

Reliability and early failure in Cu/oxide dual-damascene interconnects

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