Statistical variability and reliability in nanoscale FinFETs

Abstract

A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented. Excellent electrostatic integrity and resulting tolerance to low channel doping are perceived as the main FinFET advantages, resulting in a dramatic reduction of statistical variability due to random discrete dopants (RDD). It is found that line edge roughness (LER), metal gate granularity (MGG) and interface trapped charges (ITC) dominate the parameter fluctuations with different distribution features, while RDD may result in relatively rare but significant changes in the device characteristics.

Correlation between the Golden Ratio and Nanowire Transistor Performance

“…After conducting the DD simulations and, in turn, calibrating these in view of the MC results, the former can be used to reflect the contact resistance impacts [4]. Furthermore, it is possible to use the calibrated DD simulations to examine relative changes in I on , thus facilitating design optimization and, in addition to this, the creation of efficient statistical variability (SV) and statistical reliability (SR) simulations [12,23,24]. …”

Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability

“…The migration of advanced CMOS technology from bulk to FinFETs and FDSOI MOSFETs is driven by better electrostatic integrity and reduced random discrete dopant (RDDs) variability due to low channel doping [1]. However, the thin silicon body required by the above architectures makes them more sensitive to long-range critical dimension (CD) variations compared with bulk planar transistors.…”

“…Simultaneously some of the traditional sources of statistical variability, such as gate line edge roughness (GER) and metal gate granularity (MGG) [2] [3], can still be prominent due to the scaled transistor area. There is also a new source of statistical variability, fin edge roughness (FER), arising from stochastic local variations in the fin patterning [1] [4], which can significantly affect thin body depletion and quantum confinement [1]. It is shown that in FinFETs there is a strong interplay between the statistical variability and the processinduced variability [5], causing additional complications.…”

Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis

“…The ever increasing doping, deployed to combat short channel effects, dominates the statistical variability in bulk MOSFETs which is reaching already critical levels at 28 nm CMOS technology [14]. As a result in its 22nm technology generation Intel introduced the novel 'tri-gate' FinFET architecture [15] that has superior electrostatic integrity, tolerates low channel doping and has the potential to reduce significantly the statistical variability [16]. Fully-depleted (FD) planar SOI transistors are also introduced by ST at 28nm CMOS [17] to reduce the statistical variability.…”