STEEL: A technique for stress-enhanced standard cell library design

Abstract

Mobility degradation and device scaling limitations have led process engineers to develop new techniques that introduce mechanical stress in MOSFET channels, which results in enhanced carrier transport. New fabrication steps strive to increase carrier mobility which, consequently, increases both I on and I off in CMOS devices. However, most stress-enhancement techniques are dependent on layout parameters and their effects can be exploited within standard cell library design. In this work, we propose a new standard cell library design methodology that shares V DD and V SS source/drain connections across standard cell boundaries. Such sharing allows for increased channel stress in both the corresponding device as well as its neighboring devices. Using an industrial 65nm process and standard cell library, we show that our standard cell design methodology can be seamlessly integrated into current, state-of-the-art digital IC design flows. The new shared source/ drain technique improves critical path delay by 11% on average over a number of benchmarks for only a ~35% increase in leakage. Furthermore, stress-enhanced standard cell libraries offer a superior power/ delay tradeoff compared to dual-V th across a wide range of operating points with reduced manufacturing costs. Specifically, our stressenhanced library (with a single V th ) consumes ~2.5X less leakage than its dual-V th counterpart.

The impact of shallow trench isolation effects on circuit performance

“…Much of the literature in this area [3]- [6] is based entirely on the use of one-dimensional models that account for stress components only along the longitudinal direction (i.e., along the channel direction). However, finite element simulations in [1], [2] show that STI stress in the transverse direction, perpendicular to the channel direction, also impacts the circuit performance.…”

“…However, finite element simulations in [1], [2] show that STI stress in the transverse direction, perpendicular to the channel direction, also impacts the circuit performance. Furthermore, [3]- [6] use only a single component of the stress tensor for performance evaluation, while the entire stress tensor must be evaluated to accurately analyze STI-induced circuit performance variation. The work in [7] uses both longitudinal and transverse direction STI contributions, but is based on an empirically fitted model that is not scalable for nonrectangular shaped active/STI regions.…”

65 nm sub‐threshold logic standard cell library using quasi‐Schmitt‐trigger design scheme and inverse narrow width effect aware sizing

“…Contrary to the [29], sub‐threshold VLSI logics are implemented by exploiting unbalanced P/N network in combination with INWE sizing in [30], which is also at a loss of striking area and leakage power. Furthermore, a shared‐boundary layout design strategy is presented to increase I on ‐to‐ I off ratio in [31], achieving 11% delay improvement with 35% leakage current tradeoff. Also in [32], a layout optimisation technique is utilised for standard cells by customising the P/N ratio of each cell independently, resulting in 16% power reduction without compromising for much of the area.…”