Strain for CMOS performance improvement

Chan, V.; Rim, K.; Ieong, M.; Yang, Shu Ching; Malik, R.; Teh, Young Way; Yang, Min; Qiqing,

doi:10.1109/cicc.2005.1568758

Cited by 42 publications

(26 citation statements)

References 4 publications

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“…The channel length (L) of MOS devices is 0.15m and the channel width (W) is 1m. The test wafers were first sliced into strip along the longitudinal (parallel to the channel length) and transverse (horizontal to the channel length) directions of an MOSFET, respectively, as shown in Figure 1 [1,7]. Next, highly consistent piezoresistance coefficients were exacted for sensors at different wafer site through the four-point-bending (4PB) [10] fixture with probing facilities.…”

Section: Methodsmentioning

confidence: 99%

“…Both the literature and the theoretical analysis show that stress and/or strain lead mobility changes on a MOSFET (Metal Oxide Semiconductor Field Effective Transistor) device so that the device behaviors change at the same time [1][2][3][4][5][6][7][8]. Consequently, MOSFET has the potential to be a suitable chip stress sensor for microelectronic packaging because the measurements are nondestructive, in-situ, and real time.…”

Section: Introductionmentioning

confidence: 99%

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On the study of MOSFET micro-sensors for electronic packaging

Yang

Chao

Tseng³

et al. 2007

2007 International Conference on Electronic Materials and Packaging

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The purpose of this paper is to study the MOSFET stress sensor behaviors and to develop the related measurement methodology. With the newly developed technology, the piezoresistance coefficients of the MOSFET were extracted, and the strain and temperature effect induced MOSFET characteristics were obtained. The results of this study can be used to adjust the chip structure in a packaging so that the optimal packaging technology and material can be chosen, and accuracies of the numerical analysis can be verified through experimental data with the new technology studied in this paper.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

On the study of MOSFET micro-sensors for electronic packaging

Yang

Chao

Tseng³

et al. 2007

2007 International Conference on Electronic Materials and Packaging

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“…Hence, contacts placed farther away from the channel will increase the amount of nitride adjacent to the channel, enhancing channel stress [10]. Overall, the layout dependencies of stress are well documented [5,[9][10][11]13], but to our knowledge, no work has focused on new standard cell library design techniques which exploit these dependencies. To date, the most recent work has only suggested layout guidelines for present-day standard cell library design [10,11].…”

Section: Introductionmentioning

confidence: 98%

“…In addition to the compressive nitride liner, PMOS stress is further enhanced by embedding a layer of SiGe within the source/drain regions of a device. The lattice mismatch between SiGe and Si introduces significant stress in a PMOS channel and can increase on and off currents (I on and I off ) by as much as ~15% and ~3X, respectively [9]. The last principal stress source is the Stress Memorization Technique (SMT) used in NMOS transistors.…”

Section: Introductionmentioning

confidence: 99%

STEEL: A technique for stress-enhanced standard cell library design

Joshi¹,

Sylvester²,

Blaauw³

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Mobility degradation and device scaling limitations have led process engineers to develop new techniques that introduce mechanical stress in MOSFET channels, which results in enhanced carrier transport. New fabrication steps strive to increase carrier mobility which, consequently, increases both I on and I off in CMOS devices. However, most stress-enhancement techniques are dependent on layout parameters and their effects can be exploited within standard cell library design. In this work, we propose a new standard cell library design methodology that shares V DD and V SS source/drain connections across standard cell boundaries. Such sharing allows for increased channel stress in both the corresponding device as well as its neighboring devices. Using an industrial 65nm process and standard cell library, we show that our standard cell design methodology can be seamlessly integrated into current, state-of-the-art digital IC design flows. The new shared source/ drain technique improves critical path delay by 11% on average over a number of benchmarks for only a ~35% increase in leakage. Furthermore, stress-enhanced standard cell libraries offer a superior power/ delay tradeoff compared to dual-V th across a wide range of operating points with reduced manufacturing costs. Specifically, our stressenhanced library (with a single V th ) consumes ~2.5X less leakage than its dual-V th counterpart.

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“…These are shown compared with the existing BPSG process in Table 3. These parametric shifts were not unexpected since it is known that silicon lattice stress affects the mobility of both holes and electrons in silicon [6]. To minimize the parametric disparities, development was then directed at matching film stack characteristics, specifically relieving stress and reducing total oxide charge in the new process.…”

Section: : Yield Comparison From "Split Lot" Analysis Between the Eximentioning

confidence: 99%

A Method of Manufacturing a Low Defect, Low Stress Pre-metal Dielectric Stack for High Reliability and MEMs Applications

Naughton

Nelson

The 17th Annual SEMI/IEEE ASMC 2006 Conference

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It is widely known in the semiconductor industry that CMP induced micro-scratches can cause not only an initial failure but also a long-term reliability problem. Silicon oxide films doped with boron and phosphorus have been standard in pre-metal dielectric stacks but are prone to CMP micro scratching. A novel film stack was developed utilizing a thick undoped PECVD cap layer to mitigate device failure and reliability problems. The sequence of depositing the integral film layers in conjunction with the densification proved critical in maintaining device performance.

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Strain for CMOS performance improvement

Cited by 42 publications

References 4 publications

On the study of MOSFET micro-sensors for electronic packaging

On the study of MOSFET micro-sensors for electronic packaging

STEEL: A technique for stress-enhanced standard cell library design

A Method of Manufacturing a Low Defect, Low Stress Pre-metal Dielectric Stack for High Reliability and MEMs Applications

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