Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

Witters, L.; Mitard, J.; Loo, Roger; Demuynck, S.; Chew, Soon Aik; Schram, T.; Tao, Zheng; Hikavyy, Andriy; Sun, Jianwu; Milenin, Alexey; Mertens, Hans; Vrancken, C.; Favia, P.; Schaekers, Marc; Bender, Hugo; Horiguchi, N.; Langer, Róbert; Barla, K.; Mocuta, D.; Collaert, N.; Thean, A.

doi:10.1109/vlsit.2015.7223701

Cited by 35 publications

(26 citation statements)

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“…The uni-axial strain in Ge was confirmed by Nano Beam Diffraction (NBD) measurements. 15 The TEM cross-section along the fin shows that the dislocations are mainly confined to the Si 0.3 Ge 0.7 -SRB/Si-substrate interface. On the other hand, some stacking faults which are propagating into the Ge are visible in Figure 6b.…”

Section: Resultsmentioning

confidence: 96%

“…To investigate the strain state in more detail, reciprocal space maps (RSMs) were performed both along (longitudinal) and across (transverse) the fins. 6,15,31 RSMs measured on optimized strained Ge/Si 0.3 Ge 0.7 -SRB fins (Fig. 7), show that the single SiGe layer is relaxed in both in-plane directions while the Ge channel is fully strained w.r.t.…”

Section: Resultsmentioning

confidence: 98%

“…Additionally, we acquired reciprocal space maps (RSMs) around asymmetric reflections along and perpendicular to the fins in order to determine the lattice parameters and hence relaxation/strain values for the various layers in all three directions. 6,15,31 …”

Section: Methodsmentioning

confidence: 99%

“…Next, the Si is partly removed using either an in-situ HCl vapor etching 2,14 or an ex-situ wet chemical etching routine. 6,15 The recessed Si is replaced by the high mobility material. Subsequent oxide recess is then used to reveal the fin.…”

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confidence: 99%

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Processing Technologies for Advanced Ge Devices

Loo

Hikavyy

Witters

et al. 2016

ECS J. Solid State Sci. Technol.

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With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing. Further aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FinFET design to a nanowire FET design (also called Gate-All-Around FET). In this contribution we address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures.

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Section: Resultsmentioning

confidence: 96%

Section: Resultsmentioning

confidence: 98%

Section: Methodsmentioning

confidence: 99%

mentioning

confidence: 99%

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Processing Technologies for Advanced Ge Devices

Loo

Hikavyy

Witters

et al. 2016

ECS J. Solid State Sci. Technol.

Self Cite

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show abstract

“…The latter approach benefits from aspect ratio trapping (ART), which traps most of the TDs in the bottom part of the layer when the SRB layer thickness has an aspect ratio greater than 3 [16]. The STI processes have been extensively investigated in order to achieve similar device performances for both processes [17][18][19][20]. One advantage of the STI first process is that there is no necessity of growing a 1 μm thick SRB layer; this results in a more cost effective option compared with the STI last one.…”

Section: Introductionmentioning

confidence: 99%