Strained Si and the future direction of CMOS

Thompson, Scott E.

doi:10.1109/iwsoc.2005.99

Cited by 7 publications

(4 citation statements)

References 6 publications

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“…Table 1 lists the extracted must be provided along the transverse direction to enhance the temperature coefficients with standard deviations, and the very p-MOSFET mobility but opposite behaviors were found for close coefficients for both X and Y devices also demonstrate the longitudinal samples, it is observed that the results in this good measurement results. Table 2 merges the coefficients in subsection consist with the literatures [3][4][13][14]. Table 1, and it is found that the standard deviations are less than 500O of the extracted temperature coefficients.…”

Section: The Calibration Methodologymentioning

confidence: 83%

“…Dain | direction [3][4][5][6][7][8]. Therefore, MOSFET has the potential to be a suitable chip stress sensor for micro-electronic packaging because the measurements are nondestructive, in-situ, and real time.…”

Section: Sourcementioning

confidence: 99%

“…5 and 6. or 3. The other end of the FFC passed through a hole on the oven wall and connects to a connector which is on a AJDsa%tt = T ay(4) printed circuit board (PCB) as shown inFig. 7.…”

mentioning

confidence: 99%

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Calibrate MOSFET Micro-Stress Sensors for Electronic Packaging

Chung

Tang

Chao

et al. 2008

2008 10th Electronics Packaging Technology Conference

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are described in Second 3. Then, the validity of the new Stress measurements in microelectronic packaging through calibration methodology is demonstrated through the MOSFET devices have attracted great attentions because experimental data in Second 4. Thermal, mechanical, and the measurement is in-situ and nondestructive. In this study, a thermo-mechanical property measurements were next new assembled methodology was designed and applied so that performed respectively through the aforementioned fixture to the calibration procedures on MOSFET stress sensors can be study the stress behaviors of the devices under room and simpler and more accurate. Under mechanical, thermal, and elevated temperatures. After the experimental process, data thermo-mechanical coupling effects, parameters of the analyses were performed to study the uniformity as well as the MOSFET devices were extracted based on linear relationships applicability of the devices for stress extraction. between drain current variation and the mechanical and/or The Theoretical Model thermal effects, and the results suggested that the MOSFET In this study, the p-MOSFETs devices were fabricated devices is a useful in-situ stress sensors in electronic through standard commercialized process by TSMC (Taiwan packaging. It is concluded that the newly experimental design Semiconductor Manufacturing Company). The channel length and the extracted parameters are useful for MOSFET stress sensor's design nd applications.(L) of the MOSFET devices iS 0.15 Rtm and the channel width (W) is 1 gim. The test wafers were first sliced into strip along

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Section: The Calibration Methodologymentioning

confidence: 83%

Section: Sourcementioning

confidence: 99%

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Calibrate MOSFET Micro-Stress Sensors for Electronic Packaging

Chung

Tang

Chao

et al. 2008

2008 10th Electronics Packaging Technology Conference

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“…Both the literature and the theoretical analysis show that stress and/or strain lead mobility changes on a MOSFET (Metal Oxide Semiconductor Field Effective Transistor) device so that the device behaviors change at the same time [1][2][3][4][5][6][7][8]. Consequently, MOSFET has the potential to be a suitable chip stress sensor for microelectronic packaging because the measurements are nondestructive, in-situ, and real time.…”

Section: Introductionmentioning

confidence: 99%

On the study of MOSFET micro-sensors for electronic packaging

Yang

Chao

Tseng³

et al. 2007

2007 International Conference on Electronic Materials and Packaging

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The purpose of this paper is to study the MOSFET stress sensor behaviors and to develop the related measurement methodology. With the newly developed technology, the piezoresistance coefficients of the MOSFET were extracted, and the strain and temperature effect induced MOSFET characteristics were obtained. The results of this study can be used to adjust the chip structure in a packaging so that the optimal packaging technology and material can be chosen, and accuracies of the numerical analysis can be verified through experimental data with the new technology studied in this paper.

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Threshold voltage model for bulk strained-silicon NMOSFETs

Tinoco

García

Iñı́guez

et al. 2008

Semicond. Sci. Technol.

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In the last few years, different devices have been studied, motivated by the continuous development of microelectronics technology. One of them is the strained-silicon transistor, in search of enhanced carrier mobility. For this type of transistor, there are few works related to analytical models for the threshold voltage. Due to its importance, in this contribution we present an analytic model for the threshold voltage of n-type bulk strained-silicon transistors. The model is in terms of the technological parameters such as the strained-silicon film thickness, impurity and germanium concentrations in the silicon-germanium substrate. The validation of the voltage threshold model was done using 2D numerical simulations by ATLAS.

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Strained Si and the future direction of CMOS

Abstract: Uniaxial process induced strain is being adopted in all 90, 65, and 45 nm high performance logic technologies. Uniaxial strain offers large performance improvement at low cost and minimally increased manufacturing complexity and is scalable to future technology nodes.

Cited by 7 publications

References 6 publications

Calibrate MOSFET Micro-Stress Sensors for Electronic Packaging

Calibrate MOSFET Micro-Stress Sensors for Electronic Packaging

On the study of MOSFET micro-sensors for electronic packaging

Threshold voltage model for bulk strained-silicon NMOSFETs

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