Threshold voltage model for bulk strained-silicon NMOSFETs

Abstract

In the last few years, different devices have been studied, motivated by the continuous development of microelectronics technology. One of them is the strained-silicon transistor, in search of enhanced carrier mobility. For this type of transistor, there are few works related to analytical models for the threshold voltage. Due to its importance, in this contribution we present an analytic model for the threshold voltage of n-type bulk strained-silicon transistors. The model is in terms of the technological parameters such as the strained-silicon film thickness, impurity and germanium concentrations in the silicon-germanium substrate. The validation of the voltage threshold model was done using 2D numerical simulations by ATLAS.