Strained superjunction U-MOSFET with insulating layer between alternate pillars

Nautiyal, Payal; Naugarhiya, Alok; Verma, Shrish

doi:10.1088/2053-1591/aaff1d

Cited by 8 publications

(6 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…From figure it can be observed that the amplitude of V I P 2 and V I P 3 are more for A/S-DE-FE-TFET with TiO 2 dielectric compare to other device structures, demonstrating the better linear performance of the device. The performance of these structures can further be increased by introducing the straining effect as reported in our previous literature [40]. Finally, it can be concluded that a higher gate oxide dielectric constant is preferred for both the device analog and linearity behavior.…”

Section: Linearity Parameters Analysismentioning

confidence: 74%

Analog/RF Performance Projection of Ultra-Steep Si Doped HfO2 Based Negative Capacitance Electrostatically Doped TFET: A Process Variation Resistant Design

Singh

2021

Silicon

View full text Add to dashboard Cite

The incorporation of Si doped HfO 2 in negative capacitance electrostatically doped TFET realizes ultra-steep and process variation resistant structure. Here, Si:HfO 2 is the gate stack ferroelectric material is used in conjunction with a high-K gate dielectric HfO 2 /TiO 2 . The conceptualization of intrinsic gate voltage amplification due to the alignment of ferroelectric dipoles comprehends the negative capacitance (NC) behavior. Moreover, the work-function difference between the source/drain electrodes and the silicon induces electrostatic doping. Thus, the detrimental doping related issues, heavy doping governed mobility degradation and statistical random dopant fluctuations (RDFs) can be eliminated and it results in more process variations immune design. This work has explored the impact of the symmetric and asymmetric structure of the considered devices on both the drain and source sides, in terms of the oxide thickness between the electrodes and the Si body. Here, analog/RF performance estimation is also carried out for the parameters such as transconductance (g m ), output conductance (g d ), unity gain frequency (f T ), intrinsic gain (A V ), transconductance frequency product (TFP), and gain frequency product (GFP), etc. Our study reveals that Si:HfO 2 ferroelectric gate stack with TiO 2 dielectric shows better device performance than Si:HfO 2 ferroelectric gate stack with HfO 2 dielectric for both dc as well as ac performance.

show abstract

Section: Linearity Parameters Analysismentioning

confidence: 74%

Analog/RF Performance Projection of Ultra-Steep Si Doped HfO2 Based Negative Capacitance Electrostatically Doped TFET: A Process Variation Resistant Design

Singh

2021

Silicon

View full text Add to dashboard Cite

show abstract

“…Recently, in 2019 various techniques have been put forth to improve turn-off losses [10][11][12][13][14]. Partial carrier stored hole path structure has been suggested in order to improve turn-off loss and on-state voltage drop by 11.1% and 2.2%, respectively [12].…”

Section: Introductionmentioning

confidence: 99%

“…This technique achieves E off which is 52% as that of FS-IGBT at same breakdown and on-state voltage. To further reduce breakdown voltage (BV) and area specific on resistance (R on .A) trade-off, a layer of SiGe in p-body has been utilized along with oxide layer in between the pillar [14]. This technique offers 18% reduction in area specific on-resistance (R on ) in addition to 6% increment in BV.…”

Section: Introductionmentioning

confidence: 99%

Trench IGBT with stepped doped collector for low energy loss

Vaidya

Naugarhiya

Verma

2020

Semicond. Sci. Technol.

Self Cite

View full text Add to dashboard Cite

In this paper, a novel technique of variation doping profile in collector region for trench IGBT is proposed. The collector region is segregated in three sections such that the section with higher concentration lies towards emitter side while section with lower concentration lie towards gate side. The presence of lightly doped collector section increases the recombination rate by injecting lesser charge carrier leading to reduction in carrier lifetime. This effect further improves turn-off process for proposed device. However, due to increased recombination rate, collector current density reduces. But, this reduction is counter balanced by heavily doped collector section which injects higher charge carriers and maintains current flow through proposed device. The electrical characteristics of proposed and conventional device is simulated and analyzed. It is inferred that proposed device exhibits 48% reduction in turn-off time further minimizing energy loss by 53.3%. The lower doping profile of collector region also reduces corner electric field but due to p ++ -col section the net electric field increases hence, improving the breakdown voltage by 8.7%. Additionally, proposed structure exhibits 16.7% increment in Baliga figure of merit as compared to conventional design.

show abstract

“…Preliminary studies suggest that research is being carried out to improve the device behavior acknowledging one or the other performance parameter [6][7][8][9][10][11][12]. Introduction of workfunction engineering at the contacts [6][7][8] was found to be one of the promising technique to reduce fabrication complexity.…”

Section: Introductionmentioning

confidence: 99%

“…Introduction of workfunction engineering at the contacts [6][7][8] was found to be one of the promising technique to reduce fabrication complexity. To enhance the current flow, the employment of SiGe layer in drift as well as channel has also been explored [9,12]. For designing improved conventional vertical device, gate engineering technique has been employed [10,11].…”

Section: Introductionmentioning

confidence: 99%

Workfunction engineered stepped gate SJ UMOS with reduced specific resistance for high speed applications

Nautiyal

Naugarhiya

Verma

2019

Semicond. Sci. Technol.

Self Cite

View full text Add to dashboard Cite

In this paper, trench superjunction MOS (SJ UMOS) utilizing workfunction engineered stepped gate for performance enhancement is proposed. N + polysilicon (Φ m =4.17 eV) layer in between two P + polysilicon (Φ m =5.25 eV) layer connected by a metal gate is incorporated in the proposed device. Additionally, gate oxide thickness is increased in steps from source to drain resulting in enhanced gate-source capacitance and reduced gate-drain capacitance. The electrical behavior of conventional and proposed device is investigated using 2D numerical simulations. The results indicate 19.5% reduction in specific resistance without degrading the breakdown voltage. Further, the proposed structure also exhibits 28.9% reduction in specific gate to drain charge, 30.5% increment in gate to source charge and 54% reduction in switching delay. In addition to this, Baliga's figure of merit (BFOM) along with other technology figure of merit (FOM) has also been evaluated, demonstrating a 26% increment in BFOM. The significant improvement in FOM is attributed to reduced specific resistance and gate to drain charge of the proposed structure. Additionally, the impact of temperature on device performance is also evaluated and no degradation in the device parameters is observed.

show abstract

Strained superjunction U-MOSFET with insulating layer between alternate pillars

Cited by 8 publications

References 15 publications

Analog/RF Performance Projection of Ultra-Steep Si Doped HfO2 Based Negative Capacitance Electrostatically Doped TFET: A Process Variation Resistant Design

Analog/RF Performance Projection of Ultra-Steep Si Doped HfO2 Based Negative Capacitance Electrostatically Doped TFET: A Process Variation Resistant Design

Trench IGBT with stepped doped collector for low energy loss

Workfunction engineered stepped gate SJ UMOS with reduced specific resistance for high speed applications

Contact Info

Product

Resources

About