Strategy to optimize the development, use, and dimension of test structures to control defect appearance in backend process steps

Abstract

To inspect and classify defects occurring during backend process steps, this paper describes a comprehensive methodology how to develop, use, and dimension test structures and how to optimize their organization inside given test chip boundaries. Starting point is the description of process steps and known types of defects. According to existing design rules different test structures will be designed and arranged as (in-line) process monitors inside a checkerboard framework using standard boundary pads.

<title>Correlation between particle defects and electrical faults determined with laser scattering systems and digital measurements on checkerboard test structures</title>

“…But here the number of pads is relatively small so that methods are required to separate defects. Checkerboard test structures introduced by [Hess94], [HeSt94}, [HeWe95b] combine the large defect sensitive area inside a given pad frame and a precise defect localization.…”