Stress Buildup of Sn3.5Ag Soldered Stacked CSPs to Board-Level Drop Impact

Chen, Cheng-fu; Peterson, D.

doi:10.1109/tcpmt.2010.2100290

Cited by 3 publications

(8 citation statements)

References 38 publications

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“…In the first part of the simulation results we show the distribution of von Mises stresses in the solder balls in package U8A (which is mounted at the center of the PCB), package U15A (near the corner of the PCB, e.g., Figure 4), U10A, and U14A. The results are consistent with the previously published results [4,7]: (1) For each mounting site, the maximum stress appears at board side of the corner, bottom-level solder balls ( Figure 5 and Figure 6); (2) The largest stress is induced in the U8A package, as shown in Figure 5. We also found that the peeling stress, which is defined as the out-of-plane normal stress, is representative of the stress histogram.…”

Section: Finite Element Results Of Board-level Drop Impactsupporting

confidence: 90%

“…A bilinear plasticity model would suffice to characterize the response of lead-free (e.g., Sn3.5Ag) solder balls under high strain rate drop impact. Please refer to [4] for the discussions of selecting a plasticity model for the Sn3.5Ag alloy as the soldering material for drop impact analysis.…”

Section: Finite Element Results Of Board-level Drop Impactmentioning

confidence: 99%

“…The drop impact loading, a 0.5-ms, 1500-G, half-sine acceleration profile [6], was input at the post holes. This work only considers the 0 o orientation drop impact because it has shown that stress is more severely built up in solder balls under the 0 o orientation drop [4]. Given the 0 o drop orientation, the impact load is transmitted to the four steel posts.…”

Section: The Stacked Csp Under Modelingmentioning

confidence: 99%

“…Because this work is aimed at the structural analysis of the board-mounted assembly, the small-mass details in the solder interconnection, such as the copper pad, solder mask, polyimide layer, and pad adhesive (please refer to [4] for dimensions), have been deliberately neglected. As for the global modeling purpose, we also preliminarily modeled each solder ball into a rectangular post of 400m  400m in cross section ( Figure 4).…”

Section: The Stacked Csp Under Modelingmentioning

confidence: 99%

“…The stress-buildup in the solder balls of bilayered CSP subjected to board-level drop impact was first understood by finite element modeling [4]. It shows that the critical solder balls are at the corners of the first package level where solder balls interconnect the S-CSP to the printed circuit board (PCB).…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

The use of implicit mode functions to drop impact dynamics of stacked chip scale packaging

Chen

Wilburn

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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The dynamic response of Sn3.5Ag solder balls interconnecting bilayered chip scale packages under boardlevel drop impact is studied in this paper. The structural response of the solder balls was obtained by finite element simulations of an elastic model of board-mounted assembly under the JEDEC-defined half-sine acceleration profile. The distribution of the von Mises stress and peeling stress were examined in the critical solders.The Hilbert-Huang Transform (HHT) technique was then used to calculate the implicit mode functions (IMFs) of the dynamic response at the critical solder balls. As each IMF carries important amplitude and frequency information intrinsically retained to the processed signals, the IMFs enable a preliminary analysis about questions such as how much of the solder stress buildup is contributed from board vibrations. IntroductionThe demand in high density packaging has driven the development of stacked chip scale packages (S-CSPs) [1], such as shown in Figure 1, in which multiple CSPs are stacked and interconnected in the z-direction. To understand the stress-driven failure modes in the stacked packages, in this paper a board-mounted, bilayered stacked CSP under boardlevel drop is studied.

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Section: Finite Element Results Of Board-level Drop Impactsupporting

confidence: 90%

Section: Finite Element Results Of Board-level Drop Impactmentioning

confidence: 99%

Section: The Stacked Csp Under Modelingmentioning

confidence: 99%

Section: The Stacked Csp Under Modelingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

The use of implicit mode functions to drop impact dynamics of stacked chip scale packaging

Chen

Wilburn

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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A new methodology for board-level harmonic analysis of multi-level packages

Chen

2012

2012 IEEE 62nd Electronic Components and Technology Conference

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Design of multi-level packages for better reliability life under drop impact is often conducted through board-level drop testing. Among many failure modes associated with the board-level drop impact test, PCB pad cratering and solder joint disconnection are of particular interests. Because of the complexity and rigor in modeling and simulations, most of the present work is completed through design of experiments under a variety of board-mounting layouts and drop criteria, in order to acquire information specific to a design of interest. A new methodology is proposed to model complicated boardlevel drop impact by using the receptance theory. Receptance is defined as the ratio of a displacement response at a place to a harmonic load which is applied at the same or different place.This modeling technique enables systematically dynamic coupling and spatial coupling of the mounting board and packages. The first part of this paper is on the formulation of board-mounted multi-level packages at various locations of the mounting board, together with a solution process for the natural frequencies and vibration modes of the integrated system. Then numerical results are presented to predict the response of the assembly, and emphasis is placed on (1) the force (deformation) in the interconnections at each level between the PCB pad and packages, (2) the effect of the package's mounting location on the stresses in the solder interconnects at each level, and (3) the size effect of packages and interconnects on the deformation of interconnections at each level. The technique to be demonstrated can facilitate selection of design parameters such as the solder materials, package's mounting locations, as well as the dimensions of the mounting board, before rigorous experiments and detailed simulations. IntroductionThe design of stacked scale packages (S-CSPs) allows for better use of space for high-density packaging [1], such as the example shown in Figure 1. Among a few known reliability issues the solder interconnects in S-CSPs are vulnerable to high-stress loading, which is unavoidable under drop impact or thermal shock. To better understand the stress-driven reliability issue in the stacked packages, this paper is aimed at developing a theoretical framework for capturing the known influence factors observed in board-level drop impact testing.

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Package-on-Package Assembly Yield Assessment in the ODM/EMS Environment Using Monte Carlo Simulation

Huang

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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Package-on-package (PoP) is one of the major manufacturing strategies for achieving an electronic component miniaturization. Achieving a desired process yield is critical to maintaining competitiveness. This paper develops a scientific approach to assess the PoP assembly yield in both the x-y in-plane and the z-direction using a Monte Carlo simulation. Influences of variations of materials such as components and printed circuit boards (PCBs) are investigated. Equipment accuracy and different process strategies are also under consideration. The scenarios under which defects occur are defined through the geometric phenomena, process incidence, and theoretical inferences. Defects such as shorts and soldering open may occur after reflow soldering if there is an excessive amount of offset between the centers of the solder ball and the bonding pad during the component placement stage. The amount of component/PCB warpage during the reflow heating and coplanarity of the solder balls beneath the substrate will also impact the package stacking yield. The simulation-based design for experiment is employed to investigate the effects of soldering materials, stencil thickness, reflow temperature profile, and component ball height variation on the assembly yield. The optimal materials and process combinations are then identified.

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Stress Buildup of Sn3.5Ag Soldered Stacked CSPs to Board-Level Drop Impact

Cited by 3 publications

References 38 publications

The use of implicit mode functions to drop impact dynamics of stacked chip scale packaging

The use of implicit mode functions to drop impact dynamics of stacked chip scale packaging

A new methodology for board-level harmonic analysis of multi-level packages

Package-on-Package Assembly Yield Assessment in the ODM/EMS Environment Using Monte Carlo Simulation

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