Stress-Induced Void Formation in Metal Lines

Abstract

The problem of stress-induced voiding in the metal lines used for VLSI interconnections appeared about 10 years ago and was first reported in the literature in 1984. Some typical voids are shown in Figure 1. It is not entirely coincidental that the problem is of about the same age as the personal computer. The continuing advances in process technology that make possible the ever lower costs and improved performance of VLSI devices often have unexpected and troublesome side effects. Continuous attention to potential effects of process changes on the behavior of the materials comprising a VLSI chip is essential to avoid passing on problems to customers. The history of stress-induced voiding provides a good illustration.

Modeling of thermal stresses in metal interconnects: Effects of line aspect ratio

“…There are other factors which are important in affecting the voiding behavior, such as the availability of sites for the heterogeneous nucleation of voids and solid state reactions between Al and the surrounding coatings and dielectric. 13 Under circumstances, when these factors can be treated as independent of line geometry, the present study suggests that, by way of the evolution of hydrostatic stress, the effects of line aspect ratio on the propensity of stress-voiding damage are significant. For closely spaced Al lines (p/w less than about 3͒, an increase of the aspect ratio from below one to well above one results in a monotonically increasing voiding propensity ͑Fig.…”

“…The presence of hydrostatic tension renders metal lines thermodynamically unstable with respect to void nucleation through vacancy condensation, and voids can grow by vacancy diffusion to relieve the hydrostatic stress. 13 The magnitude of tensile hydrostatic stress is therefore an indication of the propensity of voiding damage in metal interconnects. There are other factors which are important in affecting the voiding behavior, such as the availability of sites for the heterogeneous nucleation of voids and solid state reactions between Al and the surrounding coatings and dielectric.…”

Metallurgical techniques for more reliable integrated circuits

“…Passivated Al-Cu lines are often left in a state of residual tensile stress after manufacture because of the thermal expansion mismatch between aluminum and silicon or dielectric layers. The residual stress level is often on the order of 500 MPa, 11 which is about ten times higher than the yield stress of aluminum. While stress-induced voids look similar to electromigration-induced voids and are also associated with microstructural features, the mechanism of mechanical stress-induced voiding is different from electromigration-induced voiding.…”

“…The high-temperature processes (interlevel-dielectric-layer deposition and passivation-layer deposition) play a major role in determining the residual stress level in the embedded metal lines. 11 The Al-Cu grain structure is essentially established when the hightemperature post-passivation annealing is completed. However, the reconfiguration of copper and the evolution of the Al 2 Cu precipitate distribution continue through the subsequent packaging thermal cycles.…”

Diffusional creep as a stress relaxation mechanism in electromigration

“…The physical origin of th is also unclear. Relaxation of a hydrostatic compressive stress cannot occur simply by instantaneous dislocation glide 21,22 and requires essentially some time-dependent dislocation climb, for which a sharp yield stress eludes physical meaning. Moreover, with (x)р th , hillocks would be expected to form only at xϭ0 in Fig.…”