Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application

Chen, Chien-Hao; Lee, T.L.; Hou, Tuo‐Hung; Chen, C.L.; Chen, C.C.; Hsu, J.; Cheng, Kuang-Fu; Chiu, Yu‐Jing; Tao, Hun-Jan; Jin, Y.; Diaz, C.H.; Chen, S.C.; Liang, Mong–Song

doi:10.1109/vlsit.2004.1345390

Cited by 78 publications

(10 citation statements)

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“…Capping layer films with 2.5 GPa of stress have been reported [44] making this an extremely effective and low-cost technique to introduce both longitudinal and out-of-plane channel stress [7]. The capping films are introduced either as a sacrificial layer before the source and drain anneal [59], [60] [see Fig. 10(b)] or as permanent layer post salicide [see Fig.…”

Section: Than Simentioning

confidence: 99%

“…Historically, capping layer films were not used to introduce stress since for longitudinal stress one device type improves while the other is degraded (for the standard 110 channel direction). However, many practical low cost techniques have been found to change this relationship such as wafer rotation, masked implants into locally relax the stress off one device type [4], [28], [54], [59], [60], and nonplanar raised source and drains [61]. Both the capping layers and heteroepitaxy in the source and drain introduces large components of longitudinal uniaxial stress which has added benefits over the traditional biaxial-induced substrate stress and will be described next.…”

Section: Than Simentioning

confidence: 99%

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In Search of “Forever,” Continued Transistor Scaling One New Material at a Time

Thompson

Chau

Ghani

et al. 2005

IEEE Trans. Semicond. Manufact.

162

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This work looks at past, present, and future material changes for the metal-oxide-semiconductor field-effect transistor (MOSFET). It is shown that conventional planar bulk MOSFET channel length scaling, which has driven the industry for the last 40 years, is slowing. To continue Moore's law, new materials and structures are required. The first major material change to extend Moore's law is the use of SiGe at the 90-nm technology generation to incorporate significant levels of strain into the Si channel for 20%-50% mobility enhancement. For the next several logic technologies, MOSFETs will improve though higher levels of uniaxial process stress. After that, new materials that address MOSFET poly-Si gate depletion, gate thickness scaling, and alternate device structures (FinFET, tri-gate, or carbon nanotube) are possible technology directions. Which of these options are implemented depends on the magnitude of the performance benefit versus manufacturing complexity and cost. Finally, for future material changes targeted toward enhanced transistor performance, there are three key points: 1) performance enhancement options need to be scalable to future technology nodes; 2) new transistor features or structures that are not additive with current enhancement concepts may not be viable; and 3) improving external resistance appears more important than new channel materials (like carbon nanotubes) since the ratio of external to channel resistance is approaching 1 in nanoscale planar MOSFETs. Index Terms-CMOS, metal-oxide-semiconductor field-effect transistor (MOSFET), new materials, strained silicon, very large scale integration (VLSI). Scott E. Thompson (S'87-M'87-SM'05) was an Intel Fellow, Director of Intel's 90-nm Logic Technology, and responsible for next generation process integration, transistor design, and technology yield from 1992 to 2004. He joined Intel in 1992 and worked on transistor design, circuit design, process integration, and yield on Intel's 0.35-, 0.25-, 0.18-, 0.13-, and 0.09-m advanced CMOS logic technologies. In 2004, he joined the University of Florida as an Associate Professor of electrical engineering. His current research interests include advanced transistors focusing on strained Si and Ge channel MOSFETs and carbon nanotube transistors.

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Section: Than Simentioning

confidence: 99%

Section: Than Simentioning

confidence: 99%

In Search of “Forever,” Continued Transistor Scaling One New Material at a Time

Thompson

Chau

Ghani

et al. 2005

IEEE Trans. Semicond. Manufact.

162

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show abstract

“…1). For the first and second generation strained Si MOSFETs being adopted in all high performance logic technologies [1][2][3][4][5], the industry is choosing process induced uniaxial stress due to advantages relating to n-channel threshold voltage shift and p-channel mobility enhancement at low strain and high vertical electric fields [6].…”

Section: State-of-the-art Cmosmentioning

confidence: 99%

“…2 and 4) (2) local epitaxial films grown in the source and drain regions (see Fig. 3) and (3) capping layers on top of the poly-Si gate before source/drain anneal for stress memorization of the poly-Si gate [5]. The combination of these various techniques is additive.…”

Section: State-of-the-art Cmosmentioning

confidence: 99%

Strained Si and the future direction of CMOS

Thompson

2005

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

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“…The stress memorization technique (SMT) has been used to improve NFET performance in several generations of semiconductor technology [1]. The channel stress enhancement by traditional SMT is attributed to the deformation of both poly-Si gate and amorphized source/drain (S/D) regions.…”

Section: Introductionmentioning

confidence: 99%