Stress Migration and Electromigration Improvement for Copper Dual Damascene Interconnection

Abstract

Stress migration ͑SM͒ and electromigration ͑EM͒ were widely used to study the performance of interconnection process of metal/via formation in copper dual damascene of wafers. Necking and voids at the via bottom were important in causing failures in tests of stress migration and electromigration. In this report, the contamination of the bottom of via, which results in poor step coverage, the adhesion of seed layers, and poor copper grain formation are identified to be the underlying causes of the necking and void formation after the first EM and SM tests are performed. The contamination of the via formation processes included via etching, trench etching, and barrier/seed layer depositions. A well-shaped via profile can be optimized using three methods, the first involves Cu/SiN interface stress, the second involves Cu grain growth, and the third involves post via etching clean study. Eliminating the contamination of the via bottom and optimizing step coverage and adhesion of the barrier seed layers improve the EM and SM performance from time-to-fail ϭ 13 to 59 s, in the copper-related processes for fabricating 300 mm wafers using technology that is beyond 0.13 m technology.

Design for manufacturability and reliability in extreme-scaling VLSI

“…Reduction in the failure time from EM can be worsened even further by high temperatures and mechanical stress around the vias. We can see this phenomenon in Figure 14(a) with an SEM image of the local via and wires [143]. To be more specific, Figure 14(b) shows the schematic view of metal wires, local via structure and an EM-induced void with Cu dual-damascene process.…”

Void Growth Behavior in ULSI Cu Interconnections by Grain-Boundary Diffusion Simulation

“…Therefore, SIV is recognized as a serious problem that can compromise the reliability of Cu interconnections. [4][5][6][7][8] SIV tends to be generated close to the bottom of the via holes, as shown in Fig. 1.…”

A Study of Difference in Reflow Characteristics Between Electroplated and Sputtered Cu in a Dual-Damascene Fabrication Process for Silicon Semiconductor Devices

“…These defects are recognized as a serious problem, since they degrade the electronic properties and reduce the reliability of the interconnections. [4][5][6][7][8][9][10][11] The width of the interconnections in ULSI devices is gradually shrinking; therefore, it is becoming more difficult to perfectly fill extremely small vias and trenches (with diameters or widths of 100 nm or less) by Cu electroplating.…”