Structured Analog CMOS Design

A <inline-formula> <tex-math notation="TeX">$g_{m}/I_{D}$</tex-math></inline-formula>-Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier

“…The transconductance of M 1 is constrained by the product of the unity gain bandwidth and the load capacitance. g m1 /I 1 is therefore proportional to the ratio of the unity bandwidth and the slew rate [9]. Using the slew rate of 7.5 V/μs and the load capacitance of 100 pF, the g m1 /I 1 is 16.75 S/A.…”

“…v 2 n1 , v 2 n3 , and v 2 n9 are the gate-referred noise of M 1 , M 3 , and M 9 as indicated by (9). A o is the differential gain of the folded cascode, and R out is the output resistance into M 5 and M 7…”

A high dynamic range and low power 16-channel CMOS circuit for particle detection in space plasmas

“…It offers a good trade-off between power consumption and distortion. More explanations and a detailed study of the OTA can be found in [9] [10]. Knowing that the preamplifier represents more than 50% of the total channel power consumption, the OTA Class-AB architecture seemed to us to be the best choice to develop our charge-sensitive-preamplifier.…”

A VLSI implementation of a calcium-based plasticity learning model

“…In addition, a difference in temperature between two or more transistors inside a die which can be stationary (due to devices at different distance from a heat source) or transient in time (due to a change of ambient temperature that is too fast with respect to the chip thermal time constant) together with variation of process parameters and stress result in gate voltage and current statistical mismatch. A design hint proposed in [132] states "Current mirror mismatch is proportional to g m /I Dsat ratio therefore the most favourable operation region is strong inversion, if the saturation voltage has to be minimized, the design compromise can be either the limit of strong inversion or moderate inversion operation with an increased transistor area".…”

“…A larger area reduces the voltage mismatch. In addition, given that the voltage mismatch is inversely proportional to the gm/I Dsat ratio, it decreases if the transistor operates in moderate or weak inversion [132].…”