Study of a multilevel approach to partitioning for parallel logic simulation

Subramanian, Saravanan; Rao, Dhananjai M.; Wilsey, Philip A.

doi:10.1109/ipdps.2000.846071

Cited by 11 publications

(10 citation statements)

References 24 publications

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“…In addition to investigating and implementing existing partitioning algorithms, we have developed a new partitioning algorithm based on a multilevel heuristic. The new multilevel approach [46] to partitioning attempts to optimize the concurrency, communication, and load balance factors by decoupling them into separate phases. The multilevel algorithm for partitioning has been studied and analyzed in [27] and has been shown to produce high-quality partitions (measured with respect to edges cut, i.e., the number of edges that cross partition boundaries) over several partitioning algorithms such as the inertial and the spectral bisection algorithms.…”

Section: Partitioningmentioning

confidence: 99%

“…The complexity of the multilevel algorithm is O(N E ), where N E represents the number of edges in the circuit graph making the multilevel partitioning technique a fast linear time heuristic. Further details about the multilevel partitioning algorithm are available in the literature [46]. The partitioning algorithms that have been implemented and profiled in the savant/TyVIS/warped simulation system include (a) random, (b) topological, (c) depth first search (DFS), (d) cluster (or breadth first search), (e) fanout cone, and (f) our new multilevel algorithm.…”

Section: Partitioningmentioning

confidence: 99%

See 1 more Smart Citation

Analysis and Simulation of Mixed-Technology VLSI Systems

Martin

Radhakrishnan

Rao

et al. 2002

Journal of Parallel and Distributed Computing

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Section: Partitioningmentioning

confidence: 99%

Section: Partitioningmentioning

confidence: 99%

Analysis and Simulation of Mixed-Technology VLSI Systems

Martin

Radhakrishnan

Rao

et al. 2002

Journal of Parallel and Distributed Computing

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“…[16] describes an algorithm which takes advantage of the hierarchical information present in a Verilog design. Previous efforts [21,9,1,18,22,14,20,11,13] partitioned flattened netlists of the circuits. The reason for this is that they were originally designed for floor planning (layout) and not for simulation.…”

Section: Introductionmentioning

confidence: 99%

A Multiway Partitioning Algorithm for Parallel Gate Level Verilog Simulation

Tropper

2008

2008 37th International Conference on Parallel Processing

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We describe, in this paper, a multiway partitioning algorithm for parallel gate level Verilog simulation. The algorithm is an extension of a multi-level algorithm which only creates two partitions. Like its predecessor, it takes advantage of the design hierarchy present in a Verilog circuit design. The information it makes use of is contained in the modules and their instances. The algorithm makes use of a hypergraph model of the Verilog design in which a vertex in the hypergraph represents a module instance. Our new algorithm relies upon a metric whose function is to balance the load and the communications between the modules of the Verilog design. pre-simulation is used to to evaluate the partitioning metric. When compared to hMetis, a well known multilevel partitioning algorithm, our algorithm produces a superior speedup and a reduced cut-size.

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“…Most of the partitioning algorithms [21,9,1,18,22,15,20,11,14] for distributed/parallel VLSI simulation partition gate level netlists. These algorithms are typically used for floorplanning and placement, not for simulation.…”

Section: Introductionmentioning

confidence: 99%

A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation

Tropper

2007

21st International Workshop on Principles of Advanced and Distributed Simulation (PADS'07)

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Many partitioning algorithms have been proposed for distributed VLSI simulation. Typically, they make use of a gate level netlist, and attempt to achieve a minimal cut size subject to a load balance constraint. The algorithm executes on a hypergraph which represents the netlist. In this paper we propose a design-driven iterative partitioning algorithm for Verilog based on module instances instead of gates. We do this in order to take advantage of the design hierarchy information contained in the modules and their instances. A Verilog instance represents one vertex in the circuit hypergraph. The vertex can be flattened into multiple vertices in the event that a load balance is not achieved by instance based partitioning. In this case the algorithm flattens the largest instance and moves gates between the partitions in order to improve the load balance.Our experiments show that this partitioning algorithm produces a smaller cutsize than is produced by hmetis on a gate-level netlist. It produces better speedup for the simulation because it takes advantage of the design hierarchy.

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Study of a multilevel approach to partitioning for parallel logic simulation

Abstract: Abstract

Cited by 11 publications

References 24 publications

Analysis and Simulation of Mixed-Technology VLSI Systems

Analysis and Simulation of Mixed-Technology VLSI Systems

A Multiway Partitioning Algorithm for Parallel Gate Level Verilog Simulation

A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation

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