Study of Analog/Rf and Stability Investigation of Surrounded Gate Junctionless Graded Channel MOSFET(SJLGC MOSFET)

Abstract

This paper explores the potential advantage of surrounded gate junctionless graded channel (SJLGC) MOSFET in the view of its Analog, RF performances using ATLAS TCAD device simulator. The impact of graded channel in the lateral direction on the potential, electric field, and velocity of carriers, energy band along the channel is investigated systematically. The present work mainly emphasises on the superior performance of SJLGC MOSFET by showing higher drain current (ID) , transconductance (gm) ,cut off frequency (fT) , maximum frequency of oscillation (fmax) , critical frequency (fK) .The drain current is improved by 10.03 % in SJLGC MOSFET due to the impact of grading the channel. There is an improvement in fT, fmax, fK by 45%, 29% and 18% respectively in SJLGC MOSFET showing better RF Performance. The dominance of the SJLGC MOSFET over SJL MOSFET is further elucidated by showing 74% improvement in intrinsic voltage gain (gm / gds) indicating its better applications in sub threshold region. But the transconductance generation factor of SJLGC MOSFET is less than SJL MOSFET in the subthreshold region. The intrinsic gate delay (ζD) of SJLGC MOSFET is less in comparison to SJL MOSFET due to the impact of lower gate to gate capacitance (CGG) suggesting better digital switching applications. The simulation results reveal that SJLGC MOSFET can be a competitive contender for the coming generation of RF circuits covering a broad range of operating frequencies in RF spectrum.

Analytical investigation of a triple surrounding gate germanium source metal–oxide–semiconductor field‐effect transistor with step graded channel for biosensing applications

“…The sensitivity significantly improves by using triple gates and graded doping (horizontal tri‐step doping profile) in channel. The lateral graded doping in channel improves the transconductance and decreases the drain conductance [37]. It is worth noticing that highest sensitivity is obtained in case of forward graded doping when N Ch1 = 10 10 /cm 3 , N Ch2 = 10 14 /cm 3 , and N Ch3 = 10 18 /cm 3 .…”

Circuit Level Analysis of a Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET at Nanoscale Regime

“…12 The doping concentration in the channel is maintained higher at source side and lower at drain side is referred to as graded channel (GC) FET. 13,14 This kind of doping allows for hot carrier effect (HCE) mitigation and device lifetime improvement owing to the lower drain-side doping concentration, that results in a weaker electric field near the drain region. Moreso, the ratio of localized charges and increment in drain resistance is also minimized, thereby increasing the control of channel conductance with the gate to increase its transport efficiency.…”