Study of Inherent Gate Coupling Nonuniformity of InAs/GaSb Vertical TFETs

Hsu, Chien‐Tien; Zeng, Yuping; Chang, Chen-Yen; Hu, Chenming; Chang, Edward Yi

doi:10.1109/ted.2016.2612830

Cited by 8 publications

(4 citation statements)

References 19 publications

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“…The TFETs are facing challenges due to their low ON current (I ON ), ambipolar behaviour, and higher Miller capacitances. Different TFET structures [12,13] and material systems such as SiGe, III-V semiconductor, two-dimensional-semiconducting materials [14][15][16] have been proposed to improve the performance of TFETs. Recently, an InP/InGaAs heterojunction-based T-shaped TFET (TTFET) structure has been reported [17][18][19] that improves the I ON , ambipolarity, and saturation behaviour of drain current.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of circuit performance of T‐shaped tunnel FET

Dubey

Kaushik

2020

IET Circuits, Devices & Systems

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This study investigates the analogue performance of a III-V tunnelling field-effect transistor (TFET). To explore the circuit performance of the TFET, a T-shaped TFET (TTFET) structure is investigated and its performance parameters are compared with a 14 nm simulation program with integrated circuit emphasis (SPICE)-based predictive technology model FinFET. The advantages and limitations of TTFET technology over its FinFET counterparts are discussed in detail by implementing the inverter, current mirror, track-and-hold (T/H), and differential amplifier circuits. It is observed that the TTFET inverter offers 1.56× higher maximum gain, 14.46× lower delay, and 12.13× lower-energy-delay product when compared with FinFET inverter in Fan-Out1 (FO1) configuration at V DD = 0.3 V. The TTFET-based current mirror and T/H circuit perform superior to their FinFET counterparts in terms of accuracy and delay. The TTFET-based differential amplifier provides 24.63 dB higher differential gain and 21.5 dB higher common-mode rejection ratio when compared with FinFET amplifier. Finally, the impact of the variation in process parameters on the device and circuit performance has been investigated. The standard deviation of 20% in oxide thickness, 20% in channel thickness, 20% in source doping, and 2% in metal work function results in a standard deviation 2.56% in delay of FO1 inverter from its nominal value.

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Section: Introductionmentioning

confidence: 99%

Evaluation of circuit performance of T‐shaped tunnel FET

Dubey

Kaushik

2020

IET Circuits, Devices & Systems

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“…The reason behind it is that the models presented so far [18][19][20][21] do not explain how the source/ epitaxial layer junction should be treated in calculation of tunnelling current. However, epitaxial layer-based line tunnelling devices are more promising in comparison to depletion-based line TFET structures due to their lower onset voltage and higher I ON [4][5][6][7]. Therefore, there is strong need for an analytical model of epitaxial-based line tunnelling current.…”

Section: Introductionmentioning

confidence: 99%

“…Nevertheless, the on current ( I ON ) of conventional TFETs is not comparable to the MOSFETs [2, 3]. Source‐channel junction engineering like heterojunction and line tunnelling allows higher I ON in TFETs due to the smaller effective bandgap and increased tunnelling cross‐section area [4, 5]. Therefore, a combination of these two techniques can be used to improve the device performance comparable to the MOSFET.…”

Section: Introductionmentioning

confidence: 99%

“…The target device under consideration is a recently reported InP/In 0.53 Ga 0.47 As heterojunction‐based T‐shaped TFET (TTFET) [22]. The reason behind considering TTFET is its lower ambipolar current in comparison to other epitaxial layer‐based vertical line TFET structures [5, 6]. Unlike conventional epitaxial layer‐based line tunnelling devices [7, 23, 24], TTFET shows a better saturation behaviour and allows an improvement in drain current without any increase in footprint area [22].…”

Section: Introductionmentioning

confidence: 99%

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Analytical modelling and device design optimisation of epitaxial layer‐based III–V tunnel FET

Dubey¹,

Kaushik²,

Simoen

2019

IET Circuits, Devices & Systems

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The line tunnelling and heterojunction are two important techniques to improve the performance of the tunnelling field-effect transistors (TFETs). The TFETs that utilise both of these techniques perform superior to the conventional TFETs. The recently proposed T-shaped TFET (TTFET) is one such heterojunction-based line tunnelling device that is expected to become energy efficient switch. For the first time, a physics-based analytical model for surface potential and drain current of epitaxial layer-based heterojunction line TFET has been developed. The model describes the impact of device design parameters on the electrical performance of the device. The Poisson equation is solved with precise boundary conditions to obtain the surface potential model. Kane's model is used to calculate drain current by utilising surface potential model. A good agreement between Synopsys technology computer-aided design simulation and analytical model is observed with 5.4% error in ON current at V GS = V DS = 0.5 V, an average error of 5.80% in surface potential and 7.24% in transconductance. Finally, a device design guideline is presented according to the analytical expressions.

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A review of III-V Tunnel Field Effect Transistors for future ultra low power digital/analog applications

Saravanan

Parthasarathy

2021

Microelectronics Journal

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Study of Inherent Gate Coupling Nonuniformity of InAs/GaSb Vertical TFETs

Cited by 8 publications

References 19 publications

Evaluation of circuit performance of T‐shaped tunnel FET

Evaluation of circuit performance of T‐shaped tunnel FET

Analytical modelling and device design optimisation of epitaxial layer‐based III–V tunnel FET

A review of III-V Tunnel Field Effect Transistors for future ultra low power digital/analog applications

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