Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor

Sengupta, Sarmista; Pandit, Soumya

doi:10.1080/00207217.2014.945194

Cited by 10 publications

(3 citation statements)

References 12 publications

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“…An EδDC transistor is a device structure proposed by us which is reported to be a low-power, low-cost transistor, suitable for SoC applications with controlled process variability effects due to random discrete dopant effects [12], [13], [14], [15], [16], [17]. In the present work, we derive a physics based local drain current variability model of an epitaxial delta doped channel MOS (EδDC) transistor, caused due to random fluctuation of channel length, attributed to the LER/LWR phenomenon.…”

Section: Outline and Contribution Of Our Workmentioning

confidence: 99%

A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-Channel EδDC MOS Transistor

Sengupta

Pandit

2021

Preprint

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A drain current local variability compact model due to random fluctuation of channel length induced by line edge roughness/line width roughness ( LER / LWR ) is derived here. The random fluctuation of channel length leads to correlated fluctuations of threshold voltage and effective mobility of the current carriers. Therefore, an unified compact model is required to combine all the causes. Our model is based on the principle of propagation of variance. For the model verification purpose, calibrated technology computer aided design ( TCAD ) simulation platform is extensively used for all possible bias regions and several LER profile parameters. Channel profile optimization is critically studied aiming reduction of ID variability. The model is further extended for SOI (Silicon-on-insulator) transistor and validated with literature data of threshold voltage and on-current variability.

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Section: Outline and Contribution Of Our Workmentioning

confidence: 99%

A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-Channel EδDC MOS Transistor

Sengupta

Pandit

2021

Preprint

Self Cite

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Section: Outline and Contribution Of Our Workmentioning

confidence: 99%

“…With increasing thickness of the low doped layer x 1 , depletion depth, W dm increases. Increased W dm , worsens short channel effect (SCE) [15]. Poor SCE is manifested by larger V T .…”

Section: Variation With Xmentioning

confidence: 99%

A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-channel Eδ DC MOS Transistor

Sengupta

Pandit

2021

Silicon

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A drain current local variability compact model due to random fluctuation of channel length induced by line edge roughness/line width roughness (LER/LWR) is derived here. The random fluctuation of channel length leads to correlated fluctuations of threshold voltage and effective mobility of the current carriers. Therefore, an unified compact model is required to combine all the causes. Our model is based on the principle of propagation of variance. For the model verification purpose, calibrated technology computer aided design (TCAD) simulation platform is extensively used for all possible bias regions and several LER profile parameters. Channel profile optimization is critically studied aiming reduction of I D variability. The model is further extended for SOI (Silicon-on-insulator) transistor and validated with literature data of threshold voltage and on-current variability. Keywords Epitaxial delta doped channel • line edge roughness • channel length fluctuation • propagation of variance • roughness amplitude • correlation length.

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Study of temperature variation on threshold voltage and sub-threshold slope of E $$\delta$$ δ DC MOS transistor including quantum corrections and reduction techniques

et al. 2016

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Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor

Cited by 10 publications

References 12 publications

A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-Channel EδDC MOS Transistor

A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-Channel EδDC MOS Transistor

A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-channel Eδ DC MOS Transistor

Study of temperature variation on threshold voltage and sub-threshold slope of E $$\delta$$ δ DC MOS transistor including quantum corrections and reduction techniques

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