Study of shallow trench isolation technology with a poly-Si sidewall buffer layer

Abstract

Shallow trench isolation (STI) technology with a poly-Si buffer layer at the trench sidewall has been studied. At the densification temperature of 950 • C, for the samples without using a poly-Si buffer layer, the resulting junction shows a leakage of about 700 nA cm −2 for a diode area of 100 × 100 µm 2 , primarily due to large peripheral junction leakage. The large leakage is ascribed to the defect generation caused by a thermally induced stress near the trench sidewall. The usage of a poly-Si buffer layer in the trench sidewall is found to significantly improve the junction characteristics. As a result, when a 40 nm poly-Si buffer layer is sandwiched between the Si substrate and the trench-fill silicon oxide, the resultant junctions show a leakage of only about 8 nA cm −2 . This result may reflect the considerably reduced thermally induced stress near the trench sidewall. Furthermore, at the densification temperature of 1100 • C, the usage of a poly-Si buffer layer can help to achieve excellent junctions with a leakage smaller than 5 nA cm −2 for a diode area of 100 × 100 µm 2 .