Study of thinned Si wafer warpage in 3D stacked wafers

Kim, Youngrae; Kang, Sung-Keun; Kim, Sarah Eunkyung

doi:10.1016/j.microrel.2010.05.006

Cited by 27 publications

(13 citation statements)

References 8 publications

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“…Due to the coefficient of thermal expansion (CTE) mismatch of the materials in the interposer, the warpage is induced after multiple thermal cycles during interposer fabrication processes. Warpage can lead to interfacial delamination, cracking and other reliability issues (Kim et al , 2010; Lu et al , 2009). As the size of the interposer increases, the warpage further deteriorates.…”

Section: Size and Thickness Evaluation Of Large-sized Interposermentioning

confidence: 99%

Double-sided silicon vias (DSSVs) interconnection for large-sized interposer fabrication

Yang

Dai

Cao

et al. 2023

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Purpose A large-scale detection system with more data in short time bins, small dead space and small signal identification is the ideology the scientists pursuing. These proposed demands are able to be solved by 2.5 D integration. The substance of a 2.5 D integration is called silicon interposer, which consists of the through silicon via (TSV) and redistribution layer. However, the state-of-the-art silicon interposer is not able to sustain its own mechanical strength with the detector/readout array often sitting as standalone in large science facilities and fails to reduce the expansions on the installation of the components due to its insufficient thickness and size. This study aims to propose a moderation of current interposer with large-sized, standalone properties. Design/methodology/approach This paper proposes an interposer based on double-sided silicon vias (DSSVs) interconnection. Unlike conventional interposer that is interconnected by TSVs, DSSVs interposer is interconnected by top vias (T-vias) and bottom vias (B-vias). Findings The fabrication process of DSSVs interposer is introduced, and the superiority of the double-sided interconnection process with two etch-stop layers is described in detail. The impact of different T-vias depth on DSSVs interconnections in the same wafer is discussed and two times PI opening processes are proposed to eliminate air bubbles in the B-via. The relationship between the interposer thickness and warpage is studied by finite element analysis simulation and experiment. The prototype of the DSSVs interposer with a size of 100 × 100 mm and a thickness of 318.2 µm is fabricated, and electrical tests including short tests and continuity tests are carried out. Originality/value This paper proposes a large-sized and stand-alone interposer based on DSSVs interconnection.

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Section: Size and Thickness Evaluation Of Large-sized Interposermentioning

confidence: 99%

Double-sided silicon vias (DSSVs) interconnection for large-sized interposer fabrication

Yang

Dai

Cao

et al. 2023

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“…Some amount of wafer bow is always observed on fully processed wafers, due to metal and dielectric films that are deposited on the frontside of the wafer [49,50]. The stress in thin films can be due to intrinisic stress or due to thermal mismatch stress.…”

Section: A Wafer Bowmentioning

confidence: 99%

Thin silicon wafer processing and strength characterization

Gambino

2013

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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Thin silicon die (100 um or less) are required for a number of applications, including stacked die packages and three-dimensional integrated circuits (3D-IC). The wafer thinning process is conceptually simple, but requires optimization of the backside finish and dicing to ensure high die strength. High die strength is required to minimize yield loss during assembly and to ensure high reliability during device operation. In this paper, we describe process optimization for thin wafers and thin die, and how these processes affect the fracture strength of silicon.

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“…Many studies for Cu-to-Cu wafer bonding have been explored by many researchers. [5][6][7][8][9][10][11] However, wafer warpage, coefficient of thermal expansion (CTE) mismatch with other layers in a stack, and inherent Cu process issues such as Cu oxidation, bonding surface uniformity, and Cu CMP (chemical mechanical polishing) have not been discussed in detail and it is still remained as the challenges to be resolved for Cu-to-Cu wafer bonding.…”

Section: Introductionmentioning

confidence: 99%

“…Traditionally Cu CMP is not used in electronic packaging field due to a high cost, so other planarization method like a diamond bit cutting has been reported. 8) However, high density and high performance devices still require Cu CMP.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and Challenges of Cu-to-Cu Wafer Bonding

Kang¹,

Lee²,

Kim³

et al. 2012

Journal of the Microelectronics and Packaging Society

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The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

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Study of thinned Si wafer warpage in 3D stacked wafers

Cited by 27 publications

References 8 publications

Double-sided silicon vias (DSSVs) interconnection for large-sized interposer fabrication

Double-sided silicon vias (DSSVs) interconnection for large-sized interposer fabrication

Thin silicon wafer processing and strength characterization

Fabrication and Challenges of Cu-to-Cu Wafer Bonding

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