Sub-10-nm high aspect ratio patterning of ZnO in a 500μm main field

Saifullah, Mohammad S. M.; Subramanian, K. R. V.; Anderson, David V.; Kang, Dae Joon; Huck, Wilhelm T. S.; Jones, G. A. C.; Welland, Mark E.

doi:10.1116/1.2192545

Cited by 18 publications

(12 citation statements)

References 10 publications

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“…Manufacturing single nanopores of the required diameter is not yet trivial, as can be seen from Table 1, and still beyond the capabilities of current semiconductor industry lithography techniques (45-65 nm), and even (commercially available) electron-beam lithography (5-10 nm) [6,7].…”

Section: Fabrication Methodsmentioning

confidence: 98%

Solid-State Nanopore Technologies for Nanopore-Based DNA Analysis

2007

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Nanopore-based DNA analysis is a new single-molecule technique that involves monitoring the flow of ions through a narrow pore, and detecting changes in this flow as DNA molecules also pass through the pore. It has the potential to carry out a range of laboratory and medical DNA analyses, orders of magnitude faster than current methods. Initial experiments used a protein channel for its pre-defined, precise structure, but since then several approaches for the fabrication of solid-state pores have been developed. These aim to match the capabilities of biochannels, while also providing increased durability, control over pore geometry and compatibility with semiconductor and microfluidics fabrication techniques. This review summarizes each solid-state nanopore fabrication technique reported to date, and compares their advantages and disadvantages. Methods and applications for nanopore surface modification are also presented, followed by a discussion of approaches used to measure pore size, geometry and surface properties. The review concludes with an outlook on the future of solid-state nanopores.

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Section: Fabrication Methodsmentioning

confidence: 98%

Solid-State Nanopore Technologies for Nanopore-Based DNA Analysis

2007

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“…Sub-10 nm line, trench, via, or pillar patterns were studied over fifteen years by e-beam direct writing (EBDW) nano-lithography tools or some modified SEM/TEM systems [5][6][7][8][9][10][11][12]. All of the previous methods used the high CD resolution and small beam spot size characteristics of high-KV electron beam to obtain sub-10nm patterns.…”

Section: Introductionmentioning

confidence: 99%

Sub 10-nm contact holes with aspect ratio over sixty formed by e-beam resist shrinkage techniques

2007

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E-beam chain scission resist ZEP520A with 400 nm thickness was studied for sub-10 nm contact holes with high aspect ratio formed by CD shrinkage techniques of thermal reflow and SAFIER. CD shrinkage temperatures and repeating times were process parameters to be studied. Design parameters of initial CD of 40-100 nm and line/space ratio of contact hole with 1/3 and >1/20 before shrinkage were also studied. Process window of thermal reflow for the aforementioned initial CDs is 155-165 o C while that of SAFIER is 150-165 o C. There is no shrinkage for both methods for temperatures below 140 o C. CD shrinkage rates of both methods decrease for more than one time of heating. Thermal reflow has a larger CD shrinkage rate than SAFIER. The dependence of shrinkage rate on initial CD size and spatial frequency is not apparent. CD nearly ceases shrinking for further heatings as the CD reaches an ultimate CD size. The ultimate CD for a larger initial CD is also larger. The smallest shrunk CD is found to be 5.8 nm with aspect ratio over sixty for 50 nm initial designed CD. CD uniformity also studied for both processes with 3-sigma smaller than +/-10%. The contact holes shrunk by thermal reflow process generally show funnel-shape profiles while those shrunk by SAFIER process show similar profiles with wider undercut. In summary, the thermal reflow process results in better profile while the SAFIER with slower CD shrinkage rate has a better control on CD and uniformity.

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“…Zn(NPH) shows complete decomposition at around ≈450 °C beyond which no mass loss was observed, which is consistent with previous reports. [ 54,55 ] Similarly, for Zn(NDN), the decomposition completes around ≈375 °C. Accordingly, the decomposition temperature of 500 °C, well beyond the temperature at which both the precursors complete their decomposition, was chosen as the temperature for processing the electron‐beam crosslinked precursor films.…”

Section: Resultsmentioning

confidence: 97%

“…However, due to the inherent resolution limit of photolithography‐based direct‐write techniques, majority of nanoscale ZnO devices are fabricated from routes utilizing EBL, soft‐EBL, [ 51,52 ] infiltration synthesis, [ 27,53 ] and direct‐write EBL. [ 54–56 ] In addition to the conventional acrylate based precursors, other novel precursors such as zinc naphthenate (Zn(NPH)) and zinc neodecanoate (Zn(NDN)) are also explored for fabricating nanopatterns using EBL [ 54,55 ] or direct‐write extreme UV‐interference lithography (EUV‐IL). [ 57 ] However, reports of ZnO nanowire FETs from these precursors are rather rare (one report by Jones et al.…”

Section: Introductionmentioning

confidence: 99%

Solution‐Processed High‐Performance ZnO Nano‐FETs Fabricated with Direct‐Write Electron‐Beam‐Lithography‐Based Top‐Down Route

Tiwale

Senanayak

Rubio‐Lara

et al. 2021

Adv Elect Materials

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Zinc oxide (ZnO) has been extensively investigated for use in large‐area electronics; in particular, the solution‐processing routes have shown increasing promise towards low‐cost fabrication. However, top‐down fabrication approaches with nanoscale resolution, towards aggressively scaled device platforms, are still underexplored. This study reports a novel approach of direct‐write electron‐beam lithography (DW‐EBL) of solution precursors as negative tone resists, followed by optimal precursor processing to fabricate micron/nano‐field‐effect transistors (FETs). It is demonstrated that the mobility and current density of ZnO FETs can be increased by two orders of magnitude as the precursor pattern width is decreased from 50 µm to 100 nm. These nano‐FET devices exhibit field‐effect mobility exceeding ≈30 cm2 V−1 s−1 and on‐state current densities reaching 10 A m−1, the highest reported so far for direct‐write precursor‐patterned nanoscale ZnO FETs. Using atomic force microscopy and parametric modeling, the origin of such device performance improvement is investigated. The findings emphasize the influence of pre‐decomposition nanoscale precursor patterning on the grain morphology evolution in ZnO and, consequently, open up large‐scale integration, and miniaturization opportunities for solution‐processed, high‐performance nanoscale oxide FETs.

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Sub-10-nm high aspect ratio patterning of ZnO in a 500μm main field

Cited by 18 publications

References 10 publications

Solid-State Nanopore Technologies for Nanopore-Based DNA Analysis

Solid-State Nanopore Technologies for Nanopore-Based DNA Analysis

Sub 10-nm contact holes with aspect ratio over sixty formed by e-beam resist shrinkage techniques

Solution‐Processed High‐Performance ZnO Nano‐FETs Fabricated with Direct‐Write Electron‐Beam‐Lithography‐Based Top‐Down Route

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