Submicron GaAs microwave FET's with low parasitic gate and source resistances

Bandy, S.; Chai, Yu; Chow, Robert H.; Nishimoto, C.; Zdasiuk, G.

doi:10.1109/edl.1983.25640

Cited by 20 publications

(8 citation statements)

References 8 publications

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“…The function of the T-shaped gate is to reduce the gate resistance in order to prevent the maximum frequency of oscillation and the noise characteristics from being degraded. The first time the T-shaped gate was reported, 9,10) the typical gate length was so long -around quarter micron, which is one order of the magnitude larger than today's state of the art -that the intrinsic gate delay was dominant in the total gate delay.…”

Section: Resultsmentioning

confidence: 99%

Analysis of Gate Delay Scaling in In_0.7Ga_0.3As-Channel High Electron Mobility Transistors

Fukuda

Suemitsu

Otsuji

et al. 2009

jjap

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As every year, the speaker presenting the concluding remarks has the problem of the wealth of too many interesting presentations. It is not easy to select just a few topics among many fascinating ones and any choice will be, necessarily, arbitrary. This year, I decided to make brief comments on astrophysical neutrinos, on cosmology and on gamma-ray bursts. My personal nomination for the hits of the conference goes this year to the giant flare of SGR 1806-20 (27.12.2004), which threw a new light not only on magnetars, but possibly also on a certain class of short gamma-ray bursts and to GRB 050509b − possibly the first short gamma-ray burst with a measured distance.

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Section: Resultsmentioning

confidence: 99%

Analysis of Gate Delay Scaling in In_0.7Ga_0.3As-Channel High Electron Mobility Transistors

Fukuda

Suemitsu

Otsuji

et al. 2009

jjap

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“…Substituting the measured u to eq. (2) yields that the mask opening (Li) for a V-groove with depth d is supposed to be LI =(_2xO.2O2 1.Old d (3) Thus, here comes a rule-of-thumb for 4: 1 :5 H,S04-H20,-H20 etchant: If the tip of a V-groove is desired to be located at a depth d below the substrate surface, an opening of d is needed on the mask.…”

Section: Design Considerations Of V-groove Gatesmentioning

confidence: 99%

<title>DC and rf characteristics of submicron gate FETs formed by micromachined V-groove technology</title>

1999

SPIE Proceedings

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The first In049Ga05P/GaAs/In0 2Ga8As micromachined V-groove gate doped-channel FET's (DCFET's) grown by GSMBE were proposed and fabricated successfully. The V-groove gate was formed by anisotropic wet etching of the undoped GaAs layer grown on top of device active layers, followed by standard metal evaporation and lift-off process. Owing to the outward slope of the sidewalls of micromachined V-groove, submicron effective gate length can be easily obtained by normal l-sm UV optical contact lithography. In this way, we simultaneously achieved short gate length (for high speed) and small gate resistance (for low noise) via this "mushroom-like" V-groove gate, without resorting to the expensive and timeconsuming e-beam lithography and the delicate multi-layer photoresist technique. Thanks to the inherent process simplicity, fabricated V-groove gates showed great uniformity and yield in a cost-efficient way, which is essential to industrial mass production. The fabricated DCFET's exhibited a maximum current density 'DS,max of 406 mA/mm, an external transconductance gm,e of 166 mS/mm, and a current gain cut-off frequency T of 13.9 GHz at 300K, all better than those of the counterpart DCFET's of traditional strip gates for contrast experiment. These results suggest that V-groove gate DCFET's are cost-effective devices with submicron gate FETs' performance, and are suitable for low-noise, high-speed, high-power applications.

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“…One-third micron gates have been fabricated with a triple layer PMMA/A1/PMMA structure. The aluminum spacer layer was only 200A thick (28). Finally, using a single layer of PMMA, 0.2 ~m gate GaAs MESFET's with fv = 45 GHz have been fabricated (29).…”

Section: Metalmentioning

confidence: 99%

A Review of GaAs MESFET Gate Electrode Fabrication Technologies

Weitzel

Doane

1986

J. Electrochem. Soc.

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This review is designed to give an overview of the processes that have been used to define gate electrodes for GaAs MESFET's. This is an important topic, because the size and structure of the MESFET gate basically determines the performance of the transistor, which in turn determines the performance of GaAs circuits. Therefore, considerable effort has been expended in developing a wide variety of techniques. This review covers some of these techniques: lift-off using a single layer of positive photoresist, lift-off using multilayer photoresist structures, deep UV and E-beam lithography, selfaligned processes, and some nonconventional techniques.

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Submicron GaAs microwave FET's with low parasitic gate and source resistances

Cited by 20 publications

References 8 publications

Analysis of Gate Delay Scaling in In_0.7Ga_0.3As-Channel High Electron Mobility Transistors

Analysis of Gate Delay Scaling in In_0.7Ga_0.3As-Channel High Electron Mobility Transistors

<title>DC and rf characteristics of submicron gate FETs formed by micromachined V-groove technology</title>

A Review of GaAs MESFET Gate Electrode Fabrication Technologies

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Submicron GaAs microwave FET's with low parasitic gate and source resistances

Cited by 20 publications

References 8 publications

Analysis of Gate Delay Scaling in In0.7Ga0.3As-Channel High Electron Mobility Transistors

Analysis of Gate Delay Scaling in In0.7Ga0.3As-Channel High Electron Mobility Transistors

<title>DC and rf characteristics of submicron gate FETs formed by micromachined V-groove technology</title>

A Review of GaAs MESFET Gate Electrode Fabrication Technologies

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Product

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Analysis of Gate Delay Scaling in In_0.7Ga_0.3As-Channel High Electron Mobility Transistors

Analysis of Gate Delay Scaling in In_0.7Ga_0.3As-Channel High Electron Mobility Transistors