Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs)

Kawahara, Takayuki; Horiguchi, Masashi; Kawajiri, Y.; Kitsukawa, G.; Kure, T.; Aoki, Masakazu

doi:10.1109/4.245594

Cited by 59 publications

(23 citation statements)

References 6 publications

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“…For high performance, the degenerating resistor is bypassed to ground, but during the standby state, the resistor is used to bias the source terminal of the off device. Another variation known as self-reverse biasing [Kawahara et al 1993;Sakata et al 1994] replaces the switched source impedance with another off transistor so that the equilibrium value is set through a series of "off devices." This technique was first applied to decoded word line driver circuits where the large drivers can have large leakage currents.…”

Section: Leakage Power Reductionmentioning

confidence: 99%

Challenges and design choices in nanoscale CMOS

Narendra

2005

J. Emerg. Technol. Comput. Syst.

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The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In this article, we will first review the history of technology scaling that follows Moore's law from the prespective of microprocessor designs. Challenges to continue the historical scaling trends will be highlighted and design choices to address two specific challenges, process variation and leakage power, will be discussed. In nanoscale CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in process variation and the resulting increase in design margins. Concept of adaptive circuit schemes to deal with increasing design margins will be explained. Next, with threshold voltage scaling, subthreshold leakage power has become a significant portion of total power in nanoscale CMOS systems. Therefore, it has become imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and circuit techniques to reduce system leakage will be discussed. It is essential to point out that this article does not cover all challenges that nanoscale CMOS systems face. Challenges that are not detailed in the main sections of the article and speculation on what future nanoscale silicon based CMOS systems might resemble are summarized.

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Section: Leakage Power Reductionmentioning

confidence: 99%

Challenges and design choices in nanoscale CMOS

Narendra

2005

J. Emerg. Technol. Comput. Syst.

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“…For many event driven applications, such as mobile devices where circuits spend most of their time in an idle state with no computation, stand by leakage power is especially detrimental on overall power dissipation [10]. Multi-Threshold CMOS (MTCMOS) is an effective circuit-level methodology that provides high performance in the active mode and saves leakage power during the standby mode.…”

Section: D) Reduction Technique For Leakage Powermentioning

confidence: 99%

Ultra-Low Power Designing for CMOS Sequential Circuits

Sreenivasulu¹,

Rao²,

Babu³

2015

IJCNS

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Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold voltages of the MTCMOS devices for both low and high Vth are constructed as the low threshold Vth is approximately 150 -200 mv whereas the high threshold Vth is managed by varying the thickness of the oxide Tox. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.

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“…Many other alternatives such as dual gated SOI, substrate biasing, or switched source impedance (closely related to MTC-MOS) have recently been proposed to address the conflicting requirement of high performance during active periods and low leakage during idle times [5] [6] [7] [8]. However, MTCMOS has emerged as one of the more practical solutions that can be easily implemented using minor modifications to current designs and technology.…”

Section: Introductionmentioning

confidence: 99%

Transistor sizing issues and tool for multi-threshold CMOS technology

Kao

Chandrakasan

Antoniadis

1997

Proceedings of the 34th Annual Conference on Design Automation Conference - DAC '97

128

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Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the high V t sleep transistor in an intelligent manner that trades off area and performance. In fact, many attempts at sizing the sleep transistor without close consideration of input vector patterns or internal structures can lead to large overestimates or large underestimates in sleep transistor sizing. This paper describes some of the issues involved in sizing transistors for MTCMOS and also introduces a variable breakpoint switch level simulator that can rapidly calculate delay in MTCMOS circuits as functions of design variables such as V dd , V t , and sleep transistor sizing. BACKGROUNDPower consumption in conventional CMOS circuits can be attributed to switching power, leakage power, and short circuit power. Switching power is usually the dominant term and is given by the well known formula:where α is the activity factor, C L is the total load capacitance, V dd is the supply voltage, and f clk is the clock frequency.Clearly, to reduce this energy dissipated to charge and discharge load capacitances, the circuit designer's optimum choice is to scale the supply voltage down. However, in order to maintain performance, the threshold voltage should also be scaled down as well so that the gate drive, (V gs -V t ), remains large enough, since propagation delay in a CMOS gate can be approximated as:where α is for modeling short channel effects [1] [2]. By reducing V dd , the switching power is reduced quadratically, but a reduction in V t causes an exponential increase in subthreshold leakage current. As one continues to scale down V dd and V t , the increased leakage power can dominate the dynamic switching power [3].In many event driven applications, like a processor running an X-server, circuits spend most of their time in an idle state where noPermission to make digital/hard copy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of ACM, Inc. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and /or a fee." DAC 97, Anaheim, California (c) 1997 ACM 0-89791-920-3/97/06 ..$3.50 computation is being performed, so large subthreshold leakage becomes unacceptable. Multi-threshold CMOS was developed in order to reduce this leakage current during idle modes by providing a high threshold "gating" transistor in series with the low V t circuit transistors. In active mode, the high V t transistor is turned on, while in sleep mode it is turned off, providing a small subthreshold leakage current [4]. For a purely combinational circuit, where state does not need to be preserved, only one type of high V t device is actually required. The NMOS is preferable be...

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Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs)

Cited by 59 publications

References 6 publications

Challenges and design choices in nanoscale CMOS

Challenges and design choices in nanoscale CMOS

Ultra-Low Power Designing for CMOS Sequential Circuits

Transistor sizing issues and tool for multi-threshold CMOS technology

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