Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems

Tajalli, Armin; Leblebici, Yusuf

doi:10.1109/esscirc.2009.5325939

Cited by 14 publications

(4 citation statements)

References 10 publications

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“…On the other hand,static RAM used at a slower pace, such as in applications with moderately clocked microprocessors draws very less power and can have a nearly negligible power consumption when sitting idle in the region of a few micro watts. E. Embedded use of SRAM: Static RAM in its dual ported form is used for realtime digital signal processing circuits [4]. Many categories of industrial and scientific subsystem, automotive electronics contain static random access memory.…”

Section: Writingmentioning

confidence: 99%

Review on Performance of Static Random Access Memory (SRAM)

Santhiya¹,

Mathan²

2015

International Journal of Advanced Research in Computer and Comm

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The power consumption is a major concern these days for long operational life. Although various types of techniques to reduce the power dissipation has been developed. One of the most adopted method is to lower the supply voltage. Techniques based on replica circuits which minimize the effect of operating conditions variability on the speed and power. In this paper different static random access memory are designed in order to satisfy low power, high performance circuit and the extensive survey on features of various static random access memory(SRAM) designs were reported.

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Section: Writingmentioning

confidence: 99%

Review on Performance of Static Random Access Memory (SRAM)

Santhiya¹,

Mathan²

2015

International Journal of Advanced Research in Computer and Comm

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“…The conventional 6T SRAM cell and the cells in [7], [8], [32] use differential BLs for both Read and Write operations. The cells with single Read buffer in [9]- [23], [26]- [31] use differential Write BLs (WBL) for Write operation and single Read BL for Read operation. Fig.…”

Section: Single Bl For Bl Power Savingmentioning

confidence: 99%

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Lin

Tsai

et al. 2012

IEEE J. Solid-State Circuits

156

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This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with V down to 0.35 V ( 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 µW power. Data is held down to 0.275 V with 2.29 µW Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for V around/above 1.0 V. Index Terms-Low power, low voltage, negative bit-line (BL), subthreshold SRAM cell, timing tracing.

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“…Some low-voltage operating SRAMs have been reported so far [1][2][3][4][5][6][7]. An expensive SOI device with a forward bias technique could operate at around 100MHz at half-volt [6].…”

Section: Introductionmentioning

confidence: 99%

“…However, low-cost bulk-CMOS SRAMs have come at the expense of operating speed ( Fig. 1) [1][2][3][4][5], which results in limiting application such as a sensor network.…”

Section: Introductionmentioning

confidence: 99%

0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme

Suzuki¹,

Moriwaki²,

Kawasumi³

et al. 2010

2010 Proceedings of ESSCIRC

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A low-voltage high-speed bulk-CMOS SRAM that operates over 100MHz at 0.5V, for the first time, is proposed. A novel 8-transistor (8T) memory cell with a complementary read port (C-RP) improves the read speed by enabling differential bit-line sensing, while the conventional 8T SRAM drives the bit line with a single read port (S-RP). The cell layout of the C-RP SRAM has point symmetry and a small area overhead (1.4x) compared with the conventional 6T SRAM cell, without any additional layers. The read delay and the delay variation at 0.5V were reduced by 52% and 54%, respectively, compared with the conventional S-RP 8T cell. A suspended bit-line read (SBLR) scheme is also applied to the read circuit in order to eliminate the leakage current from the unselected cells, which is an inevitable issue for a C-RP 8T cell with a conventional voltage sense amplifier (VSA).The simulated results of 1 Kbit SRAM in a 65-nm standard bulk-CMOS technology demonstrated 150-MHz operating frequency at 0.5-V single Vdd without any assist techniques. The power-delay product was reduced by 64% compared with the conventional S-RP 8T. This SRAM was implemented in test chips using 65-nm and 40-nm bulk-CMOS technologies. I.978-1-4244-6664-1/10/$26.00 ©2010 IEEE

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Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems

Cited by 14 publications

References 10 publications

Review on Performance of Static Random Access Memory (SRAM)

Review on Performance of Static Random Access Memory (SRAM)

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme

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