Printed electronics
has advanced during the recent decades in applications
such as organic photovoltaic cells and biosensors. However, the main
limiting factors preventing the more widespread use of printing in
flexible electronics manufacturing are (i) the poor attainable linewidths
via
conventional printing methods (≫10 μm),
(ii) the limited availability of printable materials (
e.g.
, low work function metals), and (iii) the inferior performance of
many printed materials when compared to vacuum-processed materials
(
e.g.
, printed vs sputtered ITO). Here, we report
a printing-based, low-temperature, low-cost, and scalable patterning
method that can be used to fabricate high-resolution, high-performance
patterned layers with linewidths down to ∼1 μm from various
materials. The method is based on sequential steps of reverse-offset
printing (ROP) of a sacrificial polymer resist, vacuum deposition,
and lift-off. The sharp vertical sidewalls of the ROP resist layer
allow the patterning of evaporated metals (Al) and dielectrics (SiO)
as well as sputtered conductive oxides (ITO), where the list is expandable
also to other vacuum-deposited materials. The resulting patterned
layers have sharp sidewalls, low line-edge roughness, and uniform
thickness and are free from imperfections such as edge ears occurring
with other printed lift-off methods. The applicability of the method
is demonstrated with highly conductive Al (∼5 × 10
–8
Ωm resistivity) utilized as transparent metal
mesh conductors with ∼35 Ω
□
at 85%
transparent area percentage and source/drain electrodes for solution-processed
metal-oxide (In
2
O
3
) thin-film transistors with
∼1 cm
2
/(Vs) mobility. Moreover, the method is expected
to be compatible with other printing methods and applicable in other
flexible electronics applications, such as biosensors, resistive random
access memories, touch screens, displays, photonics, and metamaterials,
where the selection of current printable materials falls short.