Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level

Abstract

This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of individual transistor resizing in order to achieve better cell performance (i.e. retention time, access time, and energy consumption) at the sub-VT operating level is studied. In this scenario, asymmetrically resizing the memory cell, since we modify the channel length of the write access transistor and the width of the rest of the devices in the eDRAM cell, entails a 3.5x increase in retention time as compared to the nominal case and with smaller area overhead. Moreover, such a resizing significantly improves reliability against variability and soft errors (50% and 1.9x, respectively) when the cells are operated at sub-VT level.Peer ReviewedPostprint (author's final draft

Optimization of FinFET-Based Gain Cells for Low Power Sub-VT Embedded DRAMs

“…Although the continuous device dimension reduction has been questioned 16 and it is not trivial, FinFETs may be able to continue device scaling in smaller technologies; as shown in our previous work. 17 The rest of this paper is organized as follows: Section 2 explains the device models used to simulate the Fin-FET gain-cell eDRAM and the simulation environment. Section 3 compares the performance and energy efficiency of different gain-cell eDRAM configurations.…”