Supporting systolic and memory communication in iWarp

Borkar, S.; Cohn, Robert; Cox, George W.; Groß, Thomas; Kung, H. T.; Lam, Monica S.; Levine, Margie; Moore, Brian E.; Moore, Wire; Peterson, Carl W.; Susman, Jim; Sutton, J.; Urbanski, John Paul; Webb, Jon A.

doi:10.1145/325096.325116

Cited by 92 publications

(10 citation statements)

References 10 publications

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“…Deciding whether or not to incorporate adaptive routing is still a complex costperformance tradeoff with the cost side of the equation still largely undefined. Virtual lanes provide multiple lanes for messages along any particular path in a routing algorithm 14,8]. As with adaptive rout-ing, virtual lanes can improve router performance by increasing channel utilization.…”

Section: Introductionmentioning

confidence: 99%

The Cost of Adaptivity and Virtual Lanes in aWormhole Router

Aoyama

Chien

1995

VLSI Design

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We examine the cost in router complexity of adaptivity and virtual lanes in wormhole routers, using f-flat adaptive routers (based on a generalization of planar-adaptive routing) which include routers with a range of routing freedom. Our studies show that adaptivity is expensive because it requires additional virtual channels and much larger crossbar switches for both adaptivity and deadlock prevention. Increases of 50 to 100% in channel utilization are required to justify additional degrees of routing freedom.Three internal router architectures for virtual lanes are examined and the fully expanded crossbar is found to be most effective because it gives simplest control and minimal internal blocking. Examining router designs with from 1–16 virtual lanes indicates that 30% improvements in channel utilization are required to justify each additional virtual lane. These studies combined with published simulation results indicate that only modest numbers of virtual lanes are likely to be cost effective.

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Section: Introductionmentioning

confidence: 99%

The Cost of Adaptivity and Virtual Lanes in aWormhole Router

Aoyama

Chien

1995

VLSI Design

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“…It has been widely accepted that a graph representing an interconnection network is the best candidate to serve as a virtual backbone. It has been used in some multiprocessor systems, for example, the Blue Gene/L, the Connection Machine, and the Cosmic cube …”

Section: Related Workmentioning

confidence: 99%

Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

Fan

Han

et al. 2020

Concurrency and Computation

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Network-on-chip (NoC) is a new design method of system-on-chip used in very large scale integrated circuit (VLSI) systems. It is an important issue for choosing the appropriate topology for NoC. Wirelength and layout area are significant parameters affecting NoC due to the restriction of chip area. In this paper, we propose a new interconnection network called the incomplete ternary n-cube for parallel computing systems. Then, a linear algorithm is proposed to layout incomplete ternary n-cube network onto torus NoC. Furthermore, the failure of interconnection network is also taken into account, and a fault-tolerant layout of incomplete ternary n-cube with faulty edges into torus NoC is verified. Theoretical analysis demonstrates that the proposed algorithm can reduce the network cost and wirelength, which be conducive to estimate the wire length and chip area. KEYWORDSfault tolerance, graph embedding, network-on-Chip, reconfigurable, wirelength INTRODUCTIONWith semiconductor technology entering the nanometer stage, it has become a reality for the integration of 100 billion transistors in a single chip. How to utilize a large number of transistors effectively is an important issue of the chip architecture. It has become very difficult to improve the overall performance of the system by improving the performance of the single processor core; the difficulty and complexity of chip design are also increasing. 1,2 Network-on-chip (NoC) has the advantages of high integration, low power consumption, low cost, and small volume, and it has become one of the mainstreams of very large scale integration (VLSI) system design. 3Network topology research is an important aspect of NoC. The network on chip uses the topological structure of computer network for reference. Ring-based and torus-based NoC architectures are illustrated in Figure 1 and Figure 2. Due to its own characteristics of NoC, such as a large number of available communication wire resources, a large amount of communication can be carried out between the cores, restricted by the area of the chip, and the layout of the regular network. 4,5 Therefore, NoC has certain special requirements for the topology structure.Due to the restriction of the chip area, the interconnection network and the total wire length become the crucial issues that affect the NoC communications. It is an auxiliary consideration for the cost of NoCs with respect to their interconnection networks.The more complex of networks, the higher in connectivity wiring and costs. Therefore, it is desirable to substitute a simple network for NoC with complex networks as an alternative. In such cases, one of the primary targets is improving network performance by providing better static topology features such as diameter and average distance between vertices. 6-8 Nevertheless, when designing network architecture, it is crucial to consider the influence of physical design constraints, for example wirelength, wiring congestion, and network cost. Li et al 9 studied that, in contrast to normal beliefs, NoCs suf...

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“…The concept of offline routing is not new. As early as the 1980s and 1990s, there were studies where routing decisions were preloaded into context memory to schedule the routes in their systolic arrays (Kung, 1988;Borkar et al, 1990). After that when 2D-mesh topology became popular, the author in (Shoemaker et al, 1996) applied offline routing into the 2D-mesh routing as well.…”

Section: Previous Work Of Statically-scheduled Routing Algorithmsmentioning

confidence: 99%

High Performance Communication on Reconfigurable Clusters

Sheng

Yang

Herbordt

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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High Performance Computing (HPC) has matured to where it is an essential third pillar, along with theory and experiment, in most domains of science and engineering. Communication latency is a key factor that is limiting the performance of HPC, but can be addressed by integrating communication into accelerators. This integration allows accelerators to communicate with each other without CPU interactions, and even bypassing the network stack. Field Programmable Gate Arrays (FPGAs) are the accelerators that currently best integrate communication with computation. The large number of Multi-gigabit Transceivers (MGTs) on most high-end FPGAs can provide high-bandwidth and low-latency inter-FPGA connections. Additionally, the reconfigurable FPGA fabric enables tight coupling between computation kernel and network interface. Our thesis is that an application-aware communication infrastructure for a multi-FPGA system makes substantial progress in solving the HPC communication bottleneck. This dissertation aims to provide an application-aware solution for communication infrastructure for FPGA-centric clusters. Specifically, our solution demonstrates application-awareness across multiple levels in the network stack, including low-level vii link protocols, router microarchitectures, routing algorithms, and applications. We start by investigating the low-level link protocol and the impact of its latency variance on performance. Our results demonstrate that, although some link jitter is always present, we can still assume near-synchronous communication on an FPGAcluster. This provides the necessary condition for statically-scheduled routing. We then propose two novel router microarchitectures for two different kinds of workloads: a wormhole Virtual Channel (VC)-based router for workloads with dynamic communication, and a statically-scheduled Virtual Output Queueing (VOQ)-based router for workloads with static communication. For the first (VC-based) router, we propose a framework that generates application-aware router configurations. Our results show that, by adding application-awareness into router configuration, the network performance of FPGA clusters can be substantially improved. For the second (VOQbased) router, we propose a novel offline collective routing algorithm. This shows a significant advantage over a state-of-the-art collective routing algorithm. We apply our communication infrastructure to a critical strong-scaling HPC kernel, the 3D FFT. The experimental results demonstrate that the performance of our design is faster than that on CPUs and GPUs by at least one order of magnitude (achieving strong scaling for the target applications). Surprisingly, the FPGA cluster performance is similar to that of an ASIC-cluster. We also implement the 3D FFT on another multi-FPGA platform: the Microsoft Catapult II cloud. Its performance is also comparable or superior to CPU and GPU HPC clusters. The second application we investigate is Molecular Dynamics Simulation (MD). We model MD on both FPGA clouds and clusters. We find ...

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Supporting systolic and memory communication in iWarp

Cited by 92 publications

References 10 publications

The Cost of Adaptivity and Virtual Lanes in aWormhole Router

The Cost of Adaptivity and Virtual Lanes in aWormhole Router

Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

High Performance Communication on Reconfigurable Clusters

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