Suppression of Defect Formation and Their Impact on Short Channel Effects and Drivability of pMOSFET with SiGe Source/Drain

Quasi Crystal Lindhard–Scharff–Schiott Theory and Database for Ion Implantation Profiles in Si1-xGex Substrate Based on the Theory

“…Some 300-nm-thick Si 1Àx Ge x layers were epitaxially grown on Si substrates by low-pressure chemical vapor deposition. 1) We then implanted B, P, and As ions at various energies and doses with a tilt angle of 7 and rotation angle of 0 . The Ge content ratios x of the layers were evaluated by Rutherford backscattering spectrometry (RBS), as shown in Fig.…”

“…SiGe provides enhanced carrier mobility, and is also used for the source/drain of p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) to form stress and channel regions with various content ratios x for MOSFETs processes. 1,2) Therefore, the accurate prediction of ion implantation profiles in this substrate is required. We have established a database of ion implantation profiles in Si substrates, [3][4][5][6] and database for ion implantation profiles in Ge substrates has also been investigated recently.…”

Investigation of Intermittent Haze in 300mm SiGe Epitaxy Process and its Impact on PMOS Device Performance

“…However, the selective SiGe epitaxial process is easily to produce defects like pits, haze, misfit dislocation, threading dislocation, stacking faults and mushroom like defects growth on the top of poly gate, etc. The misfit dislocation and stacking faults will degrade SiGe performance and accelerate short channel effects due to Boron diffusion and strain relaxation [2]. While the defects of stacking faults, mushroom on top poly gate and morphology can be reduced by low temperature Epi, low temperature pre-clean and recess shape control, higher quality SiGe with more compressive channel stress which results in reduced junction leakage can be obtained [3].…”

Three-Dimensional Visualization Technique for Crystal Defects in High Performance p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Embedded SiGe Source/Drain

“…4,5) Nucleation and glide of the crystal defect depend on the process conditions, such as the annealing temperature, the thickness of the SiGe film, the Ge concentration in SiGe layer and the shape of the S/D region. 6,7) Therefore, we have to control the process conditions for complementary metaloxide-semiconductor (CMOS) devices with embedded SiGe S/D. To resolve these problems, it is important to understand the complex three-dimensional geometries of the crystal defects and device architectures.…”