Suppression of erased state V/sub t/ drift in two-bit per cell SONOS memories

Roizin, Yakov; Pikhay, Evgeny; Gutman, M.

doi:10.1109/led.2004.840711

Cited by 9 publications

(3 citation statements)

References 6 publications

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“…In contrast to traditional SONOS memories, where program/erase operations involve direct electron tunneling through a thin ͑ϳ20 Å͒ bottom oxide ͑BOX͒, in NROM these operations are accomplished by hot carriers ͑electrons/holes͒ locally injected over a barrier of a relatively thick ͑40-70 Å͒ oxide into the nitride layer near the drain. 2,3 As a result, 2 bits of information can be reliably stored in a single memory transistor.…”

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Si O 2 ∕ Si 3 N 4 ∕ Al 2 O 3 stacks for scaled-down memory devices: Effects of interfaces and thermal annealing

Lisiansky

Heiman

Kovler

et al. 2006

Applied Physics Letters

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Effects of interfaces and thermal annealing on the electrical performance of the SiO 2 /Si 3 N 4 /Al 2 O 3 ͑ONA͒ stacks in nonvolatile memory devices were investigated. The results demonstrated the principal role of Si 3 N 4 /Al 2 O 3 and Al 2 O 3 /metal-gate interfaces in controlling charge retention properties of memory cells. Memory devices that employ both electron and hole trappings were fabricated using a controlled oxidation of nitride surface prior to the Al 2 O 3 growth, a high-temperature annealing of the ONA stack in the N 2 +O 2 atmosphere, and a metal gate electrode having a high work function ͑Pt͒. These devices exhibited electrical performance superior to that of their existing SiO 2 /Si 3 N 4 / SiO 2 analogs.

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“…The FN hole injection could provide an erase mechanism alternative to the currently used "hot" holes, which are the principal cause of the BOX degradation in NROM cells. [3][4][5] Moreover, the FN hole injection could enable a refresh operation of the memory cell. 15 Aluminum oxide, Al 2 O 3 , ͑k =7-10͒ ͑Ref.…”

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confidence: 99%

Si O 2 ∕ Si 3 N 4 ∕ Al 2 O 3 stacks for scaled-down memory devices: Effects of interfaces and thermal annealing

Lisiansky

Heiman

Kovler

et al. 2006

Applied Physics Letters

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“…The 3.4 nm thick bottom oxide was chosen based on ref. 14, in which excellent retention properties of the programmed state, no V T drift at room temperature and no influence of gate stress for cycled devices have been reported. For the measurements, a square pulse was applied to the gate of the SONOS cell while the substrate was grounded.…”

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confidence: 95%

A Direct Observation of the Distributions of Local Trapped-Charges and the Interface-States near the Drain Region of the Silicon–Oxide–Nitride–Oxide–Silicon Device for Reliable Four-Bit/Cell Operations

Zhang

Kim

et al. 2010

Jpn. J. Appl. Phys.

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This paper reports the direct observation of the threshold voltage shifts with trapped-charge densities as well as the interface-state densities after 10 4 program/erase (P/E) cycles at each state of the four levels in the drain edge of the silicon-oxide-nitride-oxide-silicon (SONOS) structure. We prepared a SONOS device with a 3.4-nm-thick tunnel oxide, showing 2-bit and 4-level operations at program voltages of 4 -6 V, with a 10-year retention and 10 4 P/E endurance properties. Then, by using charge pumping methods, we observed the vertical and the lateral distributions of the trapped-charges and their interface-states with the gate biases at each level of the four states in the drain edge. The trapped-charges densities at the ''10'', ''01'', and ''00'' states in the drain region were estimated to be 1:4 Â 10 12 , 3:0 Â 10 12 , and 4:9 Â 10 12 cm À2 , respectively, with a lateral width of 220 nm. The peak location of the interface-state density was shifted from the drain edge to the channel with an increase in the gate bias. These observations will be quite useful to optimize the program conditions for reliable 4-bit/cell SONOS operations.

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