Surface-Potential Solution for Generic Undoped MOSFETs With Two Gates

Shangguan, W. Z.; Zhou, Xing; Chandrasekaran, K.; Zhu, Zhengming; Rustagi, S.C.; Chiah, Siau Ben; See, Guan Huei

doi:10.1109/ted.2006.887518

Cited by 33 publications

(25 citation statements)

References 13 publications

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“…which are similar to the PB equations (in [45] and [46], respectively) for undoped body under the unipolar assumption, for which p 0 = n i and φ F = 0. Based on the general solutions in [45] and [46] for s-DG and GAA, respectively, the φ o solutions for (61a) and (61b) can be found as [8] φ o,c = v th ln B ss,c A ss,c − 2v th ln cos arccos…”

Section: Unification Of Soi/dg/gaa Modelssupporting

confidence: 63%

“…General solutions for DG/GAA MOSFETs have been studied [43][44][45][46], and most literatures are based on undoped body and one type of carrier (unipolar). Rigorous iterative φ s solution in undoped s-DG with two carriers (bipolar) has been obtained [47], which shows only a ∼nV error in φ s and a singularity in dC gg /dV g at flatband due to the unipolar assumption.…”

Section: Unification Of Soi/dg/gaa Modelsmentioning

confidence: 99%

“…Based on the general solutions in [45] and [46] for s-DG and GAA, respectively, the φ o solutions for (61a) and (61b) can be found as [8] φ o,c = v th ln B ss,c A ss,c − 2v th ln cos arccos…”

Section: Unification Of Soi/dg/gaa Modelsmentioning

confidence: 99%

“…The φ o,c (y) solution in (62) represents the ZF potential as an explicit function of the surface potential φ s,c (y) along the channel y, which is the exact solution for undoped body [45,46], the approximate solution for low-doping (small φ F ) under non-CSA, and the asymptotic solution (in strong inversion) for high-doping under CSA. It is used in UTB FD-SOI in which the ZF potential is outside the Si body, and in DG/GAA in which the ZF potential is always inside the body.…”

Section: Unification Of Soi/dg/gaa Modelsmentioning

confidence: 99%

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Unification of MOS compact models with the unified regional modeling approach

Zhou

Zhu²,

See

et al. 2011

J Comput Electron

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This paper reviews the development of the MOS-FET model (Xsim), for unification of various types of MOS devices, such as bulk, partially/fully-depleted SOI, doublegate (DG) FinFETs and gate-all-around (GAA) siliconnanowires (SiNWs), based on the unified regional modeling (URM) approach. The complete scaling of body doping and thickness with seamless transitions from one structure to another is achieved with the unified regional surface potential, in which other effects (such as those due to poly-gate doping and quantum-mechanical) can be incorporated. The unique features of the Xsim model and the essence of the URM approach are described.

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Section: Unification Of Soi/dg/gaa Modelssupporting

confidence: 63%

Section: Unification Of Soi/dg/gaa Modelsmentioning

confidence: 99%

Section: Unification Of Soi/dg/gaa Modelsmentioning

confidence: 99%

Section: Unification Of Soi/dg/gaa Modelsmentioning

confidence: 99%

See 2 more Smart Citations

Unification of MOS compact models with the unified regional modeling approach

Zhou

Zhu²,

See

et al. 2011

J Comput Electron

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“…2(b)]. First, when the applied voltage on CG goes above the threshold voltage, electrons are induced in the channel, and the electrostatic potential in the channel gradually saturates [26], [27]. More importantly, when the bended conduction band edge is lower than the Fermi level in the source, the current starts to be dominated by the source injection and cannot be further modulated by CG.…”

Section: Physical Understandingmentioning

confidence: 99%

Polarity-Controllable Silicon Nanowire Transistors With Dual Threshold Voltages

Zhang

Marchi

Sacchetto

et al. 2014

IEEE Trans. Electron Devices

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Abstract-Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential for improving circuit performance and reducing static power consumption. Here, we propose a silicon nanowire transistor with three independent GAA electrodes, demonstrating, within a unique device, a dynamic configurability in terms of both polarity and threshold voltage (V T ). This silicon nanowire transistor is fabricated using a vertically stacked structure with a top-down approach. Unlike conventional threshold voltage modulation techniques, the threshold control of this device is achieved by adapting the control scheme of the potential barriers at the source and drain interfaces and in the channel. Compared to conventional dual-threshold techniques, the proposed device does not tradeoff the leakage reduction at the detriment of the ON-state current, but only through a later turn-ON coming from a higher V T . This property offers leakage control at a reduction of loss in performance. The measured characteristic demonstrates a threshold voltage difference of ∼0.5 V between low-V T and high-V T configurations, while high-V T configuration reduces the leakage current by two orders of magnitude as compared to low-V T configuration.

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Drain current model of double-gate MOSFETs considering both electrons and holes

Zhu

Yan

et al. 2014

IEEJ Trans Elec Electron Eng

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We present a rigorously derived current solution for undoped double‐gate (DG) MOSFETs with two carriers, which is based on surface potentials. The third‐order Newton–Raphson (NR) method is used to solve the surface‐potential equations resulting from the application of the boundary conditions to the general Poisson solution, with an initial guess very close to the true solution. The results demonstrate surface‐potential solutions for DG MOSFETs with 2–7 iterations to achieve an accuracy of 10−15. The drain current model for two carriers is presented as a benchmark to test the accuracy of one‐carrier current approximation. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

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Surface-Potential Solution for Generic Undoped MOSFETs With Two Gates

Cited by 33 publications

References 13 publications

Unification of MOS compact models with the unified regional modeling approach

Unification of MOS compact models with the unified regional modeling approach

Polarity-Controllable Silicon Nanowire Transistors With Dual Threshold Voltages

Drain current model of double-gate MOSFETs considering both electrons and holes

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