Surviving the end of frequency scaling with reconfigurable dataflow computing

Abstract

Over the past decade x86 processors have come to dominate the world's largest supercomputers. However in the future conventional multicore processors are unlikely to be able to deliver the necessary performance per $ and per W to achieve exascale performance. Heterogeneous computing is emerging as a powerful alternative to conventional multi-core to help address these challenges. In this paper we describe our approach to Maximum Performance Computing -building applicationspecific computers which complement conventional x86 processors with high performance dataflow engines implemented on FPGA to provide 10-100x improvements in performance and performance/W. We describe the MaxCompiler programming system which allows software engineers to create dataflow engines optimized for their particular applications, and discuss an example application that has been accelerated using this methodology.

A reconfigurable fabric for accelerating large-scale datacenter services

“…The Convey HC-2 [8], Maxeler MPC series [21], BeeCube BEE4 [5] and SRC MAPstation [25] are all examples of commercial FPGA acceleration appliances. While the appliance model appears to be an easy way to integrate FPGAs into the datacenter, it breaks homogeneity and reduces overall datacenter flexibility.…”

dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs

“…The platform constitutes of a hardware implementation, a compiler from a high-level dataflow language, MaxJ, to FPGA bitstream, and a runtime environment. MaxJ [22] provides explicit control of the design of the hardware architecture itself, which is critical in delivering good performance and effectively exploiting customisation opportunities available for FPGA designers. It is conceptually close to Verilog, but with increased productivity due to the abstraction of low-level vendor IPs; MaxJ provides good support for software-only simulation and interfacing with many available programming languages.…”

VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks

“…The latest A11 Bionic application processor or Apple is one example, Manuscript which includes a dedicated hardware module for the ANN. Typical speed-ups between 30-200x over SW implementations have been reported [1]. Traditional Hardware Description Languages (HDLs) like VHDL and Verilog, provide mechanisms to parameterize descriptions.…”