Synergistic fault-tolerance for memory chips

SEVA: A Soft-Error- and Variation-Aware Cache Architecture

“…Existing work [13][14] making use of SECDED have limitation that they improve defect tolerance at the expense of degraded tolerance against soft errors. SEVA can overcome such a limitation.…”

“…There have been proposals that combine a redundancy technique with ECC to tolerate a high number of random defects [13] [14]. ECC, usually SECDED, is maintained for each data block.…”

“…While the error detection and correction capability of ECC can be enhanced by using codes that are more powerful than SECDED, these codes incur significant overheads and are impractical for being implemented in high-speed SRAMs. Previous work therefore improves defect tolerance at the expense of degraded soft error tolerance [13] [14]. This paper proposes SEVA, a Soft Error and Variation Aware cache architecture.…”

“…The number of variation-induced defective memory cells becomes high with device scaling [6] [2], leading the conventional redundancy techniques (e.g., using redundancy rows/columns) to become impractical. Combination of a redundancy technique with ECC can tolerate a high degree of random defects [13] [14]. A block containing a single defective cell can be repaired by ECC.…”

Cost models for large file memory DRAMs with ECC and bad block marking

“…The IBM 16-Mb ECC DRAM [9] used a Hamming code to increase the reliability against soft errors and to correct hard errors. In addition to providing on-chip SEC-DED coding and decoding circuitry (based on an ECC similar to a modified Hamming code), the IBM design kept with conventional practice and also provided both redundant rows and columns.…”