Synergistic integration of dynamic cache reconfiguration and code compression in embedded systems

Optimization techniques are widely used in embedded systems design to improve overall area, performance and energy requirements. Dynamic cache reconfiguration (DCR) is very effective to reduce energy consumption of cache subsystems. Finding the right reconfiguration points in a task and selecting appropriate cache configurations for each phase are the primary challenges in phase-based DCR. In this paper, we present a novel intra-task dynamic cache reconfiguration technique using a detailed cache model, and tune a highly-configurable cache on a per-phase basis compared to tuning once per application. Experimental results demonstrate that our intra-task DCR can achieve up to 27% (12% on average) and 19% (7% on average) energy savings for instruction and data caches, respectively, without introducing any performance penalty. 1

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“…These techniques are referred as inter-task DCR. Studies have shown that inter-task DCR can achieve significant energy savings [2].…”

Section: Introductionmentioning

confidence: 99%

Intra-Task Dynamic Cache Reconfiguration

Hajimiri

Mishra

2012

2012 25th International Conference on VLSI Design

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“…Hajimiri et al [92] integrate cache reconfiguration and code compression to improve both performance and energy efficiency of embedded systems. For a single-level cache hierarchy, their technique performs exhaustive exploration of the cache design space by varying different parameters such as line size, associativity and total size; and simulating each one of the resultant configuration.…”

Section: Saving Energy In Specific Componentsmentioning

confidence: 99%

“…Microarchitectural techniques for saving energy in specific components e.g. main memory ( [82][83][84]), cache [6,16,35,[85][86][87][88][89][90][91][92][93][94][95][96][97][98][99][100][101][102][103], scratchpad memory [104], TLB [105] or making other changes to memory hierarchy e.g. adding extra components [106,107].…”

Section: Overviewmentioning

confidence: 99%

A survey of techniques for improving energy efficiency in embedded computing systems

Mittal¹

2014

IJCAET

135

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Recent technological advances have greatly improved the performance and features of embedded systems. With the number of just mobile devices now reaching nearly equal to the population of earth, embedded systems have truly become ubiquitous. These trends, however, have also made the task of managing their power consumption extremely challenging. In recent years, several techniques have been proposed to address this issue. In this paper, we survey the techniques for managing power consumption of embedded systems. We discuss the need of power management and provide a classification of the techniques on several important parameters to highlight their similarities and differences. This paper is intended to help the researchers and application-developers in gaining insights into the working of power management techniques and designing even more efficient high-performance embedded systems of tomorrow.

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“…To achieve additional amount of energy saving, cache energy saving techniques have been synergistically integrated with some other approaches, such as DVFS (dynamic voltage/frequency scaling) [36], [90], [109], [114]- [116], data compression [83], [106], [117], [118], prefetching [119], etc. Further, cache leakage energy saving has also been discussed in the context of QoS (quality-of-service) systems [24], [26], real-time systems [98], [99], [120] and embedded multitasking systems [97], [99], [121], [122] etc.…”

Section: A Overviewmentioning

confidence: 99%

A survey of architectural techniques for improving cache power efficiency

Mittal

2014

Sustainable Computing: Informatics and Systems

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Synergistic integration of dynamic cache reconfiguration and code compression in embedded systems

Cited by 10 publications

References 14 publications

Intra-Task Dynamic Cache Reconfiguration

Intra-Task Dynamic Cache Reconfiguration

A survey of techniques for improving energy efficiency in embedded computing systems

A survey of architectural techniques for improving cache power efficiency

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