Synopsys' open educational design kit: Capabilities, deployment and future

Goldman, Rich; Bartleson, Karen; Wood, Troy; Kranen, Kevin; Chun, Cao; Melikyan, Vazgen; Markosyan, G.

doi:10.1109/mse.2009.5270840

Cited by 56 publications

(15 citation statements)

References 1 publication

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“…The first publicly-available PDK, FreePDK45, was jointly developed by North Carolina State University (NCSU) and Oklahoma State University (OSU), based a 45nm predictive technology models [23]. Subsequently, several open-source PDKs are developed across 7nm to 180nm CMOS technologies, including Synopsys Generic Libraries 14nm, 28/32nm, 90nm [11], [24], Cadence University Program 45nm, 90nm, 180nm [12], ASAP PDK 7nm [13], and FreePDK 15nm [14], and 45nm [15]. There are improved versions of FreePDK with new add-on devices, such as RRAM [25] and MTJ [26].…”

Section: B Open-source Pdks and Opportunitiesmentioning

confidence: 99%

FreePDK15TFET: An Open-Source Process Design Kit for 15nm CMOS and TFET devices

Chen

Zhang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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With Moore's law reaching its limits, the use of new materials or new devices' structure has emerged as the next generation of CMOS devices. Among all, tunneling field-effect transistors (TFETs) have achieved a steep sub-threshold slope of less than 60mV/decade yet there is a lack of a complete process design kit (PDK) for large-scale circuit design. Hence, we present an open-source 15nm TFET PDK (15nmTFETPDK), which is based on FreePDK15 with additional support for open-source TFET models and its associated Cadence Virtuoso pcell in OA format and Mentor Calibre physical verification files. Our users can design their circuit in the Cadence Virtuoso platform and verify the consistency of the drawn layout and the circuit through the Calibre Platform. We hope that this open-source PDK allows them to further advance their research with new emerging devices.

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Section: B Open-source Pdks and Opportunitiesmentioning

confidence: 99%

FreePDK15TFET: An Open-Source Process Design Kit for 15nm CMOS and TFET devices

Chen

Zhang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Synthesis and place and route were done with the Synopsys suite (Synopsys, 2013) and a 90nm standard cell library (Goldman, Bartleson, Wood, Kranen, Cao, Melikyan, &Markosyan, 2009). Delay and power consumption analysis were done with the Prime Time tool of the Synopsys suite.It allowsto analyze delay and power consumption at gate level and layout level.…”

Section: B Synthesis and Simulation Environmentsmentioning

confidence: 99%

On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis

Dupuis

Natale

Flottes

et al. 2013

Information Security Journal: A Global Perspective

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Hardware TrojanHorses (HTHs) are malicious and stealthy alterations of integrated circuits introduced at design or fabrication steps in order to modify the circuit's intended behavior when deployed in the field. Due to HTHs stealth and diversity(intended alteration, implementation, triggering conditions), detecting and/or locating them is a challenging task. SeveralHTHs detection approaches have been proposed to address this problem.This paper focuses on so-called "side-channel analysis" methods,i.e.,methods that use power or delay measurements to detect potential HTHs. Itreviews these methods and raises some considerations about the experiments made to evaluate them. Moreover, an original case studyis presented in which we show that weak experiments may lead to misleading interpretations. Last, we evoke problems inherent to actual power and delay measurements.

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“…To investigate the effect of delay increase due to IR-drop, we conducted several experiments on ITC'99 b14 benchmark circuit [16] with 5,419 cells layout. The layout was designed using Synopsys SAED90nm EDK Digital Standard Cell Library with 1.2V power supply voltage [17]. To see as much IR-drop variation as possible, power distribution network was designed with two pads placed on upper right and lower left corners, a power ring, and no power straps.…”

Section: Preliminary Experimentsmentioning

confidence: 99%

A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation

Yamato

Yoneda

Hatayama

et al. 2012

2012 IEEE International Test Conference

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In return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel percell dynamic IR-drop estimation method. Instead of performing time-consuming IR-drop analysis for each pattern one by one, the proposed method uses global cycle average power profile for each pattern and dynamic IRdrop profiles for a few representative patterns, thus total computation time is effectively reduced. Experimental results on benchmark circuits demonstrate that the proposed method achieves both high accuracy and high time-efficiency.

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Synopsys' open educational design kit: Capabilities, deployment and future

Cited by 56 publications

References 1 publication

FreePDK15TFET: An Open-Source Process Design Kit for 15nm CMOS and TFET devices

FreePDK15TFET: An Open-Source Process Design Kit for 15nm CMOS and TFET devices

On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis

A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation

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