Synthesis of a new manufacturable high-quality graded gate oxide for sub-0.2 μm technologies

Roy, P.K.; Chen, Yuanning; Chetlur, S.

doi:10.1109/16.944191

Cited by 7 publications

(6 citation statements)

References 18 publications

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“…Figure 3 shows the results of estimating (a) the density of SiO 2 , (b) interface roughness and (c) D it of H 2 -annealed samples. The POA process reduced the interface roughness, as previously reported by Roy et al (6), and it also reduced D it . These effects are likely to help suppress NBTI.…”

Section: Influence Of Hydrogen and Effect Of Post-oxidation Anneal On...supporting

confidence: 80%

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Bias Temperature Instability Characterization of Advanced Gate Stacks

Fujieda¹,

Terai²,

Saitoh³

et al. 2007

ECS Trans.

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We performed a physical and electrical characterization of the defects that would cause negative and positive bias temperature instability (NBTI, PBTI) in gate stacks that use SiO2, plasma-nitrided SiO2, HfSiON, and HfSiON with Ni- silicide electrodes. The characterization shows that the influence of impurities, damages and mechanical stress, derived from the newly incorporated materials and process technologies on the insulator bulk and insulator/Si interface must be suppressed to cope with the problems of NBTI and PBTI in the advanced gate stacks.

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Section: Influence Of Hydrogen and Effect Of Post-oxidation Anneal On...supporting

confidence: 80%

“…Although "A" was assumed to be related to H 2 O from the NBTI dependence on oxide's wetness, this assumption does not seem to be fully verified. Roy et al showed that postoxidation anneal (POA) process can reduce NBTI (6). If the above H-related model is valid, a change in the H distribution induced by POA should be observed.…”

Section: Introductionmentioning

confidence: 99%

Bias Temperature Instability Characterization of Advanced Gate Stacks

Fujieda¹,

Terai²,

Saitoh³

et al. 2007

ECS Trans.

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“…88 It was shown by Roy et al that it is beneficial to grow the gate oxide at a temperature above the SiO 2 viscoelastic temperature. 89 Growth stress incorporation in SiO 2 is the result of SiO 2 viscosity decrease at high growth temperatures and its subsequent increase during cooling. A graded structure aids in stress relaxation, where a pre-grown oxide layer provides grading for the subsequent high-temperature oxide layer to grow below the pregrown seed SiO 2 layer.…”

Section: Temperaturementioning

confidence: 99%

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

Schroder

Babcock

2003

Journal of Applied Physics

940

396

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Articles you may be interested inInterface traps responsible for negative bias temperature instability in a nitrided submicron metal-oxidesemiconductor field effect transistor Appl. Phys. Lett. 98, 103513 (2011); 10.1063/1.3559223 Bias temperature instability in metal-oxide-semiconductor field-effect transistors with atomic-layer-deposited Sinitride/ Si O 2 stack gate dielectrics J. Appl. Phys. 103, 084512 (2008); 10.1063/1.2907768Using the Hall effect to measure interface trap densities in silicon carbide and silicon metal-oxide-semiconductor devices Appl.A study on the capacitance-voltage characteristics of metal-Ta 2 O 5 -silicon capacitors for very large scale integration metal-oxide-semiconductor gate oxide applications Identification of isolation-edge related random telegraph signals in submicron silicon metal-oxide-semiconductor field-effect transistors

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“…This new oxide considerably improves the hope of scaling SiO 2 below 1.6 nm in a manufacturing environment. 13 …”

Section: Gate Oxidationmentioning

confidence: 97%

A review: Thermal processing in fast ramp furnaces

Roy¹,

Merchant²,

Kaushal

2001

Journal of Elec Materi

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INTRODUCTIONMany of the semiconductor manufacturing steps require thermal processing for the deposition and growth of films, induction of reactions, and annealing of defects by energetic processes such as implantation and plasma processing. Historically, thermal processing steps during silicon (Si) wafer fabrication have been carried out in a furnace. A furnace depends on equilibrium heat-transfer conditions to ensure uniform heating of wafers placed in it. This limits the rate of temperature rise in the furnace due to limitations governing uniform heat transfer across each wafer placed in the furnace. Most of the furnaces normally maintain a constant temperature across the flat zone (less than 0.25°C 1 ). Such temperature accuracy enables molecular level control of the process chemistry that relates directly to precise film thickness, junction depth, and dopant concentrations. Such a level of consistent processing across large wafer batches can be directly linked to yield device parameter consistency and gives a significant advantage over a nonisothermal cold-wall technology. Rapid thermal processing (RTP), on the other hand, operates in an inherently transient mode where the various components of the reactor are not in thermal equilibrium with each other.Conventional furnaces have relatively small ramp rates (3-10°C/min) compared to RTP (500-1000°C/ min), but furnaces can typically process 100-150 wafers at the same time, while rapid thermal processors are single-wafer type. In order to combine the best features of furnaces and rapid thermal processors, equipment vendors have developed the fast thermal processor. The fast thermal processor uses a standard vertical furnace configuration with a batch size of up to 100 wafers and an enhanced heating and cooling capability to achieve ramp rates up to 200°C/min. Special heater elements have been designed for these fast thermal processors, permitting a higher operating temperature for the heater element. This improved furnace hardware increases the ramp-up (heating) and ramp-down (cooling) rates to reduce overall processing time and cost-ofownership (COO). 2 Because there are practical limits to the scaling of both time and temperature, single-wafer RTP is not practical for processes such as field oxides or drivein anneals. Additionally, the amount of wafer handling required between the load lock, process chamber, and cool down stage can put serious demands on automation and can quickly become the limiting factor for throughput. Two major issues associated with batch processing are the thermal budget and within-wafer temperature uniformity. These issues can be addressed by reducing the wafer load in a single batch, by increasing boat pitch (spacing between wafers), and by increasing the ramp rate. With a smaller batch size, the temperature ramp rate can be increased. With an increased pitch, tem-The capabilities and advantages of advanced batch furnaces in meeting semiconductor process requirements (up to a minimum of 100 nm technology node) are reviewed. Hot wall ba...

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Synthesis of a new manufacturable high-quality graded gate oxide for sub-0.2 μm technologies

Cited by 7 publications

References 18 publications

Bias Temperature Instability Characterization of Advanced Gate Stacks

Bias Temperature Instability Characterization of Advanced Gate Stacks

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

A review: Thermal processing in fast ramp furnaces

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