Synthesis of High Quality n-type CdSe Nanobelts and Their Applications in Nanodevices

Abstract

Cd-enriched ambient, high quality n-type CdSe nanobelts (NBs) with various electron concentrations (from ∼1016 to 1018 cm−3), which can meet different device requirements, were synthesized via the chemical vapor deposition (CVD) method. The electron mobilities are much higher than those reported previously for CdSe one-dimensional (1D) nanostructures. High performance single CdSe NB field effect transistors (NB-FETs) and CdSe NB/p +-Si heterojunction light emitting diodes (HLEDs) are fabricated and studied. The NB-FETs have the best performance among the reported CdSe 1D nano-FETs with an on−off ratio of ∼3 × 108, a threshold voltage of ∼−4.1 V, and a maximum transconductance of ∼1.49 μS. The room temperature electroluminescence spectra of the HLEDs consist of only an intense CdSe band-edge emission peak (∼708 nm) with a full width at half-maximum of about 29 nm.

Structural control of photoconductive CdSe nanostructures through a Bi-assisted VLS process

“…4(f) shows the gating behaviors of top-gated CdSe NW FET under white light. The source-drain current I ds increased as the gate bias V g increased from -30 V to 30 V, indicating an n-type 6 behavior as reported previously [12]. Our CdSe NW devices exhibited a transconductance (g m = dI ds /dV g ) of ~8.98 nS and an on/off ratio (I on /I off ) of ~3.91  10 2 , for V ds = 1 V under white light.…”

Outermost tensile strain dominated exciton emission in bending CdSe nanowires

“…The CdSe nanowires used here were synthesized via chemical vapor deposition method [25]. The CdSe nanowires have single crystal wurtzite structure and grow along the [0001] direction with diameter ranging from 200 nm to 1 μm.…”

Field-Effect Transistors from Lithographically Patterned Cadmium Selenide Nanowire Arrays

“…Electrical characteristics of pc-CdSe NWFETs were measured using a Keithley 2400 sourcemeter and a Keithley 428 current amplifier both controlled by LabVIEW software. The source-drain current, I sd , was measured as a function of the source-drain voltage, V sd , at gate voltages, V g , ranging from −10 to 60 V. Values of the transconductance, g m , and the threshold voltage, V th , were determined from I sd versus V gs curves using the linear region of these curves 25,27 = g dI dV m sd gs (1) For CdSe nanowires with a rectangular cross section, the gate capacitance per unit length can be calculated using eq 2 52 …”