Synthesis of operation-centric hardware descriptions

Abstract

Most hardware description frameworks, whether schematic or textual, use cooperating finite state machines (CFSM) as the underlying abstraction. In the CFSM framework, a designer explicitly manages the concurrency by scheduling the exact cycle-by-cycle interactions between multiple concurrent state machines. Design mistakes are common in coordinating interactions between two state machines because transitions in different state machines are not semantically coupled. It is also difficult to modify one state machine without considering its interaction with the rest of the system. This paper presents a method for hardware synthesis from an "operation centric" description, where the behavior of a system is described as a collection of "atomic" operations in the form of rules. Typically, a rule is defined by a predicate condition and an effect on the state of the system. The atomicity requirement simplifies the task of hardware description by permitting the designer to formulate each rule as if the rest of the system is static.An implementation can execute several rules concurrently in a clock cycle, provided some sequential execution of those rules can reproduce the behavior of the concurrent execution. In fact, detecting and scheduling valid concurrent execution of rules is the central issue in hardware synthesis from operation-centric descriptions. The result of this paper shows that an operation-centric framework offers significant reduction in design time, without loss in implementation quality.

Hardware synthesis from a recursive functional language

“…Like FLaSH, resource sharing is a focus of Bluespec [14], a hardware description language with a strong functional influence (e.g., higher-order functions, polymorphism). Bluespec's most distinctive feature is its use of "rules"-guarded atomic actions that are scheduled by a synthesized rule scheduler.…”

High-level modeling and FPGA prototyping of microprocessors

“…We choose an experimental operation-centric language [10] over mainstream RTL-based languages (e.g. RTL subset of Verilog or VHDL) to deal with the complexity of microprocessor designs.…”

Designing a reorder buffer in bluespec

“…Bluespec has been used at Sandburst, MIT and CMU to describe complex hardware, Previous work has also shown that small but complex designs described using TRS, the formalism underlying Bluespec, are amenable to formal verification [I], It has also been shown that a simple 5-stage MIPS pipeline can be synthesized from TRS's quite effciently [7,8] , What remains to be seen is if the correctnesscentric Bluespec design approach is able to generate RTL that is comparable to handwritten Verilog.…”