Synthesis of QDI Combinational Circuits using Null Convention Logic Based on Basic Gates

Abstract

Currently, synchronous digital circuits (SDC) may require certain design conditions, such as power consumption, robustness, performance, etc. These design conditions are more difficult to satisfy when SDC are implemented in VLSI (Very Large Scale Integration) technology and in the deep-sub-micron MOS (DSM-MOS) technology. The asynchronous design style has properties that serve as an alternative to design DSM-MOS technology circuits and it can satisfy these design conditions. Quasi Delay-Insensitive (QDI) circuits is a class of asynchronous circuits, they have properties where the DSM-MOS technology design is applied, because they are robust to noise, temperature and voltage variations, as well as low electromagnetic emissions, and they are tolerant to certain faults. An interesting style of QDI combinational circuits are NCL (NULL Convention Logic) circuits, because they accept conventional Boolean functions and it can achieve a better optimization. This paper presents an approach and an architecture based in basic gates for the synthesis of NCL gates, therefore its implementation uses only standard libraries and Field Programmable Gate Array (FPGA). The proposed QDI combinational circuits are implemented in the approach that uses only NCL gates.