Synthesis of Runtime Switchable Pareto Buffers Offering Full Range Fine Grained Energy/Delay Trade-Offs

Abstract

This paper presents a formalized synthesis methodology for variable tapered buffer chains achieving Pareto optimal Energy-Delay (E/D) trade-offs. Much work has been done for variable tapered buffer chain design explicitly targeting energy (and/or area) minimization for a given timing constraint. In contrast this work presents an automated methodology capable of providing all existing variable tapered buffer configurations achieving Pareto optimal trade-offs in the E/D space for the full feasible range of these two metrics together with a discussion of the practically achievable trade-off range. We also provide a practical case study that illustrates the application of our techniques in load dominated logical blocks such as decoders, drivers in SRAMs and Register Files (RF) as well as interconnect buffers. We have validated our design technique via SPICE simulations based on 65 and 32 nm CMOS technology and applied it for the design and fine tuning of run-time switchable buffers within these blocks, confirming that a very wide range in delay and energy reduction (up to 30%) can be achieved when compared to solely speed optimized buffer design.