Synthesizing Tiled Matrix Decomposition on FPGAs

Tai, Yi-Gang; Psarris, Kleanthis; Lo, Chia-Tien Dan

doi:10.1109/fpl.2011.91

Cited by 8 publications

(12 citation statements)

References 16 publications

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“…Similar concepts as in this paper for FPGA implementation and design of a unified, area-efficient unit that can perform the necessary computations (division, square root and inverse square root operations that will be discussed later) for calculating Householder QR factorization is presented in [11]. Finally, a tiled matrix decomposition based on blocking principles is presented in [12].…”

Section: Related Workmentioning

confidence: 99%

Floating Point Architecture Extensions for Optimized Matrix Factorization

Pedram

Gerstlauer

Geijn

2013

2013 IEEE 21st Symposium on Computer Arithmetic

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Abstract-This paper examines the mapping of algorithms encountered when solving dense linear systems and linear leastsquares problems to a custom Linear Algebra Processor. Specifically, the focus is on Cholesky, LU (with partial pivoting), and QR factorizations. As part of the study, we expose the benefits of redesigning floating point units and their surrounding datapaths to support these complicated operations. We show how adding moderate complexity to the architecture greatly alleviates complexities in the algorithm. We study design trade-offs and the effectiveness of architectural modifications to demonstrate that we can improve power and performance efficiency to a level that can otherwise only be expected of full-custom ASIC designs.A feasibility study shows that our extensions to the MAC units can double the speed of required vector-norm operations while reducing energy by 60%. Similarly, up to 20% speedup with 15% savings in energy can be achieved for LU factorization. We show how such efficiency is maintained even in the complex inner kernels of these operations.

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Section: Related Workmentioning

confidence: 99%

Floating Point Architecture Extensions for Optimized Matrix Factorization

Pedram

Gerstlauer

Geijn

2013

2013 IEEE 21st Symposium on Computer Arithmetic

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“…We survey recent work on tall-skinny QR factorization on parallel architectures like multi-cores [7], GPUs [8] and FPGAs [9]. While the performance of multi-cores is good for square matrices (90 GFLOPs with 58.8% efficiency), it decreases signficantly for tall-skinny matrices (2 GFLOPs with 1.2% efficiency) .…”

Section: Related Workmentioning

confidence: 99%

“…Recently, Tai et.al. [9] presented an architecture comprising linear array of processing elements (PEs) for the Householder QR targeting large square matrices. Each PE is responsible for computing an iteration of the outer loop in Algorithm 1.…”

Section: Parallel Architecture For Householder Qrmentioning

confidence: 99%

“…This paper presents a custom architecture for TSQR which bridges the performance gap that still exists between the parallel potential available in TSQR and that which has been exploited by mapping on variety of parallel architectures like multi-cores [7], Graphical Processing Units (GPUs) [8] and Field Programmable Gate Arrays (FPGAs) [9]. In order to motivate, we show the performance scaling trends for QR factorization as a function of matrix width in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…• Quantitative comparison with a custom architecture for FPGA proposed in [9] and a highly optimized GPUbased implementation in [8] showing a speedup of 0.57× -7.7× (2.2 × geo.mean) and 3.38× -12.70× (6.47× geo.mean) respectively.…”

Section: Introductionmentioning

confidence: 99%

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Enhancing performance of Tall-Skinny QR factorization using FPGAs

Rafique

Kapre

Constantinides

2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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Communication-avoiding linear algebra algorithms with low communication latency and high memory bandwidth requirements like Tall-Skinny QR factorization (TSQR) are highly appropriate for acceleration using FPGAs. TSQR parallelizes QR factorization of tall-skinny matrices in a divideand-conquer fashion by decomposing them into sub-matrices, performing local QR factorizations and then merging the intermediate results. As TSQR is a dense linear algebra problem, one would therefore imagine GPU to show better performance. However, the performance of GPU is limited by the memory bandwidth in local QR factorizations and global communication latency in the merge stage. We exploit the shape of the matrix and propose an FPGA-based custom architecture which avoids these bottlenecks by using high-bandwidth on-chip memories for local QR factorizations and by performing the merge stage entirely on-chip to reduce communication latency. We achieve a peak doubleprecision floating-point performance of 129 GFLOPs on Virtex-6 SX475T. A quantitative comparison of our proposed design with recent QR factorization on FPGAs and GPU shows up to 7.7× and 12.7× speed up respectively. Additionally, we show even higher performance over optimized linear algebra libraries like Intel MKL for multi-cores, CULA for GPUs and MAGMA for hybrid systems.

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Algorithm/Architecture Codesign of Low Power and High Performance Linear Algebra Compute Fabrics

Pedram

2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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Synthesizing Tiled Matrix Decomposition on FPGAs

Cited by 8 publications

References 16 publications

Floating Point Architecture Extensions for Optimized Matrix Factorization

Floating Point Architecture Extensions for Optimized Matrix Factorization

Enhancing performance of Tall-Skinny QR factorization using FPGAs

Algorithm/Architecture Codesign of Low Power and High Performance Linear Algebra Compute Fabrics

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